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* Add PoC of Arm DRTM specification version Beta-0topics/arm-drtm-pocLucian Paul-Trifu2022-03-0948-184/+3518
| | | | Change-Id: I26e6f2d4b2299edc246f5e8504d5d15b1399f640
* Merge changes I10b5cc17,I382d599f into integrationv2.5Madhukar Pappireddy2021-05-172-3069/+142
|\ | | | | | | | | | | * changes: docs(prerequisites): add `--no-save` to `npm install` fix(hooks): downgrade `package-lock.json` version
| * docs(prerequisites): add `--no-save` to `npm install`Chris Kay2021-05-171-1/+1
| | | | | | | | | | | | | | | | | | To avoid the mistake fixed by the previous commit, ensure users install the Node.js dependencies without polluting the lock file by passing `--no-save` to the `npm install` line. Change-Id: I10b5cc17b9001fc2e26deee02bf99ce033a949c1 Signed-off-by: Chris Kay <chris.kay@arm.com>
| * fix(hooks): downgrade `package-lock.json` versionChris Kay2021-05-171-3068/+141
| | | | | | | | | | | | | | | | | | | | | | The NPM lock file was accidentally updated using a later version of Node.js than required by the prerequisites. This upgraded the lock file to the v2 format, which causes a warning on Node.js 14 (the prerequisites version). This moves the lock file back to v1 by installing the dependencies with Node.js 14. Change-Id: I382d599fd2b67b07eb9234d14e7b631db6b11453 Signed-off-by: Chris Kay <chris.kay@arm.com>
* | Merge "feat(makefile): incrementing minor version to reflect v2.5 release" ↵Madhukar Pappireddy2021-05-141-1/+1
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| * | feat(makefile): incrementing minor version to reflect v2.5 releaseMadhukar Pappireddy2021-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | | Updated the minor version in the makefile Change-Id: Ie2b3ce5b36a105a0e2fff52c3740cc9702ca3108 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | Merge "docs(juno): update TF-A build instructions" into integrationbipin.ravi2021-05-141-21/+28
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| * | | docs(juno): update TF-A build instructionsZelalem2021-05-121-21/+28
| |/ / | | | | | | | | | | | | | | | | | | | | | Clean up instructions for building/running TF-A on the Juno platform and add correct link to SCP binaries. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I536f98082e167edbf45f29ca23cc0db44687bb3b
* | | Merge "docs: spm design document refresh" into integrationOlivier Deprez2021-05-144-479/+452
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| * | | docs: spm design document refreshOlivier Deprez2021-05-124-479/+452
| |/ / | | | | | | | | | | | | | | | | | | General refresh of the SPM document. Change-Id: I2f8e37c3f34bc8511b115f00b9a53b6a6ff41bea Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
* | | Merge "build(hooks): update Commitizen to ^4.2.4" into integrationJoanna Farley2021-05-132-3552/+753
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| * | build(hooks): update Commitizen to ^4.2.4Chris Kay2021-05-122-3552/+753
| |/ | | | | | | | | | | | | | | | | | | An indirect dependency of Commitizen (`merge`) is currently failing the NPM.js auditor due to vulnerability CVE-2020-28499. This commit moves the minimum version of Commitizen to 4.2.4, which has resolved this vulnerability. Change-Id: Ia9455bdbe02f7406c1a106f173c4095943a201ed Signed-off-by: Chris Kay <chris.kay@arm.com>
* | Merge "docs(release): add change log for v2.5 release" into integrationMadhukar Pappireddy2021-05-131-1/+670
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| * docs(release): add change log for v2.5 releaseMadhukar Pappireddy2021-05-071-1/+670
| | | | | | | | | | | | | | Change log for trusted-firmware-a v2.5 release Change-Id: I6ffc8a40d2cc3a18145b87f895acdc1400db485a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | Merge "fix(plat/arm_fpga): increase initrd size" into integrationv2.5-rc1Mark Dykes2021-05-071-1/+1
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| * | fix(plat/arm_fpga): increase initrd sizeAndre Przywara2021-05-051-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | In the comment in the ARM FPGA DT we promise a generous 100 MB initrd, but actually describe only a size of 20 MB. As initrds are the most common and easy userland option for the boards, let's increase the maximum size to the advertised 100 MB, to avoid unpacking errors when an initrd exceeds the current limit of 20 MB. Change-Id: If08ba3fabdad27b2c2aff93b18c3f664728b4348 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge "docs: removing "upcoming" change log" into integrationMark Dykes2021-05-052-150/+0
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| * | docs: removing "upcoming" change loglaurenw-arm2021-05-052-150/+0
| |/ | | | | | | | | | | | | | | Removing the "Upcoming" change log due to the change in change log processing. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I6d2cc095dca3e654bd7e6fec2077c58bfbc48bb5
* | Merge "docs: revert FVP versions for select models" into integrationMark Dykes2021-05-041-2/+2
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| * docs: revert FVP versions for select modelslaurenw-arm2021-05-041-2/+2
|/ | | | | | | | Reverting FVP versions to previous version 11.12.38 for Cortex-A32x4 and Neoverse-N2x4. Change-Id: I81e8ad24794dd425a9e9a66dc8bb02b42191abf1 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* Merge "docs: update list of supported FVP platforms" into integrationv2.5-rc0Lauren Wehrmeister2021-04-301-4/+7
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| * docs: update list of supported FVP platformslaurenw-arm2021-04-301-4/+7
| | | | | | | | | | | | | | | | Updated the list of supported FVP platforms as per the latest FVP release. Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* | Merge "docs(threat model): add TF-A threat model" into integrationbipin.ravi2021-04-306-2/+889
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| * | docs(threat model): add TF-A threat modelZelalem2021-04-306-2/+889
|/ / | | | | | | | | | | | | | | | | | | | | This is the first release of the public Trusted Firmware A class threat model. This release provides the baseline for future updates to be applied as required by developments to the TF-A code base. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I3c9aadc46196837679f0b1377bec9ed4fc42ff11
* | Merge "plat/st: do not rely on tainted value for dt property length" into ↵Manish Pandey2021-04-301-6/+5
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| * | plat/st: do not rely on tainted value for dt property lengthYann Gautier2021-04-291-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To compare the "okay" string of a property, strncmp is used but with the length given by fdt_getprop. This len value is reported as tainted by Coverity [1]. We just can use strlen("okay") which is a known value to compare the 2 strings. [1] https://scan4.coverity.com/reports.htm#v51972/p11439/fileInstanceId=96515154&defectInstanceId=14219121&mergedDefectId=342997 Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Ic8fb6ccf3126a37df615e433eb028861812015da
* | | Merge changes from topic "imx8mp_fix" into integrationManish Pandey2021-04-302-4/+4
|\ \ \ | | | | | | | | | | | | | | | | | | | | * changes: plat: imx8mp: change the bl31 physical load address plat: imx8m: Fix the macro define error
| * | | plat: imx8mp: change the bl31 physical load addressJacky Bai2021-04-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K, currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will leave the last 64KB in non-continuous space. To provide a continuous 384KB + 64KB space for generic use, so move the BL31 space to 0x970000-0x990000 range. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I96d572fc0f87f05a60f55e0552a68b6e70f8e7f4
| * | | plat: imx8m: Fix the macro define errorJacky Bai2021-04-301-2/+2
|/ / / | | | | | | | | | | | | | | | | | | the 'always_on' member should be initialized from 'on'. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I5746ff40075b4fcda2ac7d04a8d7f1269af17e91
* | | Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integrationManish Pandey2021-04-304-12/+38
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0 plat: ti: k3: board: Lets cast our macros plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing plat: ti: k3: platform_def.h: Define the correct number of max table entries plat: ti: k3: board: lite: Increase SRAM size to account for additional table
| * | | plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0Nishanth Menon2021-03-262-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ENABLE_PIE (position independent executable) is default on K3 platform to handle variant RAM configurations in the system. This, unfortunately does cause confusion while reading the code, so, lets make things explicit by selecting 0x0 as the "SEC_SRAM_BASE" out of which we compute the BL31_BASE depending on usage. Lets also document a warning while at it to help folks copying code over to a custom K3 platform and optimizing size by disabling PIE to modify the defaults. Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I8e67a9210e907e266ff6a78ba4d02e3259bb2b21
| * | | plat: ti: k3: board: Lets cast our macrosNishanth Menon2021-03-262-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lets cast our macros to the right types and reduce a few MISRA warnings. Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I0dc06072713fe7c9440eca0635094c5f3ceb7f1c
| * | | plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computingNishanth Menon2021-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We compute BL31_END - BL31_START on the fly, which is basically BL31_SIZE. Lets just use the BL31_SIZE directly so that we dont complicate PIE relocations when actual address is +ve and -ve offsets relative to link address. Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I5e14906381d2d059163800d39798eb39c42da4ec
| * | | plat: ti: k3: platform_def.h: Define the correct number of max table entriesNishanth Menon2021-03-261-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we are using static xlat tables, we need to account for exact count of table entries we are actually using. peripherals usart, gic, gtc, sec_proxy_rt, scfg and data account for 6 entries and are constant, however, we also need to account for: bl31 full range, codebase, ro_data as additional 3 region With USE_COHERENT_MEM we do add in 1 extra region as well. This implies that we will have upto 9 or 10 regions based on USE_COHERENT_MEM usage. Vs we currently define 8 regions. This gets exposed with DEBUG=1 and assert checks trigger, which for some reason completely escaped testing previously. ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:97 BACKTRACE: START: assert Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I962cdfc779b4eb3b914fe1c46023d50bc289e6bc
| * | | plat: ti: k3: board: lite: Increase SRAM size to account for additional tableNishanth Menon2021-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We actually have additional table entries than what we accounted for in our size. MAX_XLAT_TABLES is 8, but really we could be using upto 10 depending on the platform. So, we need an extra 8K space in. This gets exposed with DEBUG=1 and assert checks trigger, which for some reason completely escaped testing previously. ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:97 BACKTRACE: START: assert Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I5c5d04440ef1fccfaf2317066f3abbc0ec645903
* | | | Merge "feat(tc0): update Matterhorn ELP DVFS clock index" into integrationOlivier Deprez2021-04-301-1/+1
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| * | | | feat(tc0): update Matterhorn ELP DVFS clock indexUsama Arif2021-04-301-1/+1
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the the Matterhorn ELP Arm core to operate at its designated OPP. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I7ccef0cfd079d630c3cfe7874590bf42789a1dca
* | | | Merge "docs: remove PSA wording for SPM chapters" into integrationOlivier Deprez2021-04-305-17/+15
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| * | | | docs: remove PSA wording for SPM chaptersOlivier Deprez2021-04-305-17/+15
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | PSA wording is not longer associated with FF-A. Change-Id: Id7c53b9c6c8f383543f6a32a15eb15b7749d8658 Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
* | | | Merge "revert(commitlint): disable `signed-off-by` rule" into integrationOlivier Deprez2021-04-301-1/+1
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| * | | revert(commitlint): disable `signed-off-by` ruleChris Kay2021-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The `signed-off-by` rule does not correctly detect the `Signed-off-by:` trailer if it's not the last trailer. Therefore, this rule has been disabled until we can resolve this in the commitlint upstream. Change-Id: I50ea29067528f3c1c25beeea5eb25134b25b2af2 Signed-off-by: Chris Kay <chris.kay@arm.com>
* | | | Merge changes from topic "fw-update" into integrationOlivier Deprez2021-04-2910-7/+146
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | * changes: docs: add build options for GPT support enablement feat(plat/arm): add GPT parser support
| * | | docs: add build options for GPT support enablementManish V Badarkhe2021-04-292-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Documented the build options used in Arm GPT parser enablement. Change-Id: I9d7ef2f44b8f9d2731dd17c2639e5ed0eb6d0b3a Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
| * | | feat(plat/arm): add GPT parser supportManish V Badarkhe2021-04-298-8/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added GPT parser support in BL2 for Arm platforms to get the entry address and length of the FIP in the GPT image. Also, increased BL2 maximum size for FVP platform to successfully compile ROM-enabled build with this change. Verified this change using a patch: https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/9654 Change-Id: Ie8026db054966653b739a82d9ba106d283f534d0 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | | | Merge changes I15e7cc43,Id7411bd5,I92bafe70,I8f1c0658 into integrationManish Pandey2021-04-2918-63/+240
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: stm32mp1: enable PIE for BL32 stm32mp1: set BL sizes regardless of flags Add PIE support for AARCH32 Avoid the use of linker *_SIZE__ macros
| * | | | stm32mp1: enable PIE for BL32Yann Gautier2021-04-214-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to prepare future support of FIP, BL32 (SP_min) is compiled as Position Independent Executable. Change-Id: I15e7cc433fb03e1833002f4fe2eaecb6ed42eb47 Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
| * | | | stm32mp1: set BL sizes regardless of flagsYann Gautier2021-04-211-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BL2 size is set to 100kB, and BL32 to 72kB, regardless of OP-TEE or stack protector flags. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Id7411bd55a4140718d64a647d81037720615fc81
| * | | | Add PIE support for AARCH32Yann Gautier2021-04-219-18/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just stubbed with _pie_fixup_size=0. The changes are an adaptation for AARCH32 on what has been done for PIE support on AARCH64. The RELA_SECTION is redefined for AARCH32, as the created section is .rel.dyn and the symbols are .rel*. Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | | Avoid the use of linker *_SIZE__ macrosYann Gautier2021-04-215-17/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The use of end addresses is preferred over the size of sections. This was done for some AARCH64 files for PIE with commit [1], and some extra explanations can be found in its commit message. Align the missing AARCH64 files. For AARCH32 files, this is required to prepare PIE support introduction. [1] f1722b693d36 ("PIE: Use PC relative adrp/adr for symbol reference") Change-Id: I8f1c06580182b10c680310850f72904e58a54d7d Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | | | | Merge "refactor(plat/arm): replace FIP base and size macro with a generic ↵Mark Dykes2021-04-287-14/+14
|\ \ \ \ \ | | |/ / / | |/| | | | | | | | name" into integration
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