| Commit message (Collapse) | Author | Age | Files | Lines |
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This patch adds some documentation improvements in response to out-of-box
usability testing:
* Provide targetted links to other parts of the documentation.
* Clarify which toolchain is required.
* Clarify where the FVP binary and the bl1.bin and fip.bin files can be found
* Remove comment that cache state modelling is disabled in the known
limitations, since it is now supported and enabled.
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I0b1d889c17edb5a40c4ed81c2a58c593258c3139
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This patch fixes a cache flush issue for `bl2_ep_info`. With this fix,
we can run FVP with cache state modelling enabled for testing TFTF and
TRP.
Change-Id: Id525d29d43f58b25dd1f44b40d29e7693fc56e4a
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: John Powell <john.powell@arm.com>
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This patch updates FVP parameters for the new
dual-cluster model. It also updates the DTS
path when building TF-A.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: Iaefc0620a41e1206d8af5035752b7e75544e4b16
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Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: I57a788153ec01458b1626007ba18ae9b22cc3b72
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This patch updates the build system to support the ENABLE_RME
build flag option.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7a145a2812fdf812e5b6353a35412c3bffe84fba
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This patch makes changes in the platform files needed to enable the
RME extension. There are DTB changes included.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I0f229f0848475dcd9d2f796bf62eb32156358a30
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The following is introduced in the patch
1. Enable GPT translation tables
2. Adds a new context for Realm world and adds realm world awareness in context management
3. Initializes CPU registers in context management for Realm world
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I5bc8f3413144fb63d9eb4f5885abdcf5a44b4db1
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This patch introduces the RMM dispatcher into BL31. This
will be the mechanism that will enable communication to
take place between the Realm and non secure world. Currently
gives the capability for granules to be transitioned from
non secure type to realm and vice versa.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I70155b4df0f71ff576da98a627a0a46bb462688c
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Adding Testing Realm Payload. This is the realm
dummy payload that is loaded as default if the RMM
is not loaded into BL32. There are basic SMC
calls supported which include version request and
granule transition that is exercised from TFTF.
This is communicated to RMMD via SMC calls
from non secure world.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I489cb145866f05bb30dd4802a98464024af02fbf
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This patch enables BL2 to run in root world (EL3) which is
needed as per the security model of RME-enabled systems.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I53ace51e326fcdd44d44c791a7cb9ffaa20ed3f5
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This patch adds the granule partition table library code. It will be
updated later to be more flexible, as the current implementation is
very rigid.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I523e247bdb373595131469f5226f0680514fcffe
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This patch makes the necessary changes in the Xlat framework as well as
some general architectural changes needed in RME-enabled systems.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I1953de15fc9b8d10a6b2eead100513729f66e2ea
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* changes:
docs(prerequisites): add `--no-save` to `npm install`
fix(hooks): downgrade `package-lock.json` version
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To avoid the mistake fixed by the previous commit, ensure users install
the Node.js dependencies without polluting the lock file by passing
`--no-save` to the `npm install` line.
Change-Id: I10b5cc17b9001fc2e26deee02bf99ce033a949c1
Signed-off-by: Chris Kay <chris.kay@arm.com>
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The NPM lock file was accidentally updated using a later version of
Node.js than required by the prerequisites. This upgraded the lock file
to the v2 format, which causes a warning on Node.js 14 (the
prerequisites version). This moves the lock file back to v1 by
installing the dependencies with Node.js 14.
Change-Id: I382d599fd2b67b07eb9234d14e7b631db6b11453
Signed-off-by: Chris Kay <chris.kay@arm.com>
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into integration
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Updated the minor version in the makefile
Change-Id: Ie2b3ce5b36a105a0e2fff52c3740cc9702ca3108
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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Clean up instructions for building/running TF-A on the
Juno platform and add correct link to SCP binaries.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I536f98082e167edbf45f29ca23cc0db44687bb3b
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General refresh of the SPM document.
Change-Id: I2f8e37c3f34bc8511b115f00b9a53b6a6ff41bea
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
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An indirect dependency of Commitizen (`merge`) is currently failing the
NPM.js auditor due to vulnerability CVE-2020-28499. This commit moves
the minimum version of Commitizen to 4.2.4, which has resolved this
vulnerability.
Change-Id: Ia9455bdbe02f7406c1a106f173c4095943a201ed
Signed-off-by: Chris Kay <chris.kay@arm.com>
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Change log for trusted-firmware-a v2.5 release
Change-Id: I6ffc8a40d2cc3a18145b87f895acdc1400db485a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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In the comment in the ARM FPGA DT we promise a generous 100 MB initrd,
but actually describe only a size of 20 MB.
As initrds are the most common and easy userland option for the boards,
let's increase the maximum size to the advertised 100 MB, to avoid
unpacking errors when an initrd exceeds the current limit of 20 MB.
Change-Id: If08ba3fabdad27b2c2aff93b18c3f664728b4348
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Removing the "Upcoming" change log due to the change in change log
processing.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I6d2cc095dca3e654bd7e6fec2077c58bfbc48bb5
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Reverting FVP versions to previous version 11.12.38 for Cortex-A32x4
and Neoverse-N2x4.
Change-Id: I81e8ad24794dd425a9e9a66dc8bb02b42191abf1
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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Updated the list of supported FVP platforms as per the latest FVP
release.
Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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This is the first release of the public Trusted
Firmware A class threat model. This release
provides the baseline for future updates to be
applied as required by developments to the
TF-A code base.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I3c9aadc46196837679f0b1377bec9ed4fc42ff11
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integration
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To compare the "okay" string of a property, strncmp is used but with the
length given by fdt_getprop. This len value is reported as tainted by
Coverity [1]. We just can use strlen("okay") which is a known value
to compare the 2 strings.
[1] https://scan4.coverity.com/reports.htm#v51972/p11439/fileInstanceId=96515154&defectInstanceId=14219121&mergedDefectId=342997
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ic8fb6ccf3126a37df615e433eb028861812015da
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* changes:
plat: imx8mp: change the bl31 physical load address
plat: imx8m: Fix the macro define error
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on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,
currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will
leave the last 64KB in non-continuous space. To provide a continuous
384KB + 64KB space for generic use, so move the BL31 space to
0x970000-0x990000 range.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I96d572fc0f87f05a60f55e0552a68b6e70f8e7f4
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the 'always_on' member should be initialized from 'on'.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I5746ff40075b4fcda2ac7d04a8d7f1269af17e91
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* changes:
plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
plat: ti: k3: board: Lets cast our macros
plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing
plat: ti: k3: platform_def.h: Define the correct number of max table entries
plat: ti: k3: board: lite: Increase SRAM size to account for additional table
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ENABLE_PIE (position independent executable) is default on K3
platform to handle variant RAM configurations in the system. This,
unfortunately does cause confusion while reading the code, so, lets
make things explicit by selecting 0x0 as the "SEC_SRAM_BASE" out of
which we compute the BL31_BASE depending on usage.
Lets also document a warning while at it to help folks copying code
over to a custom K3 platform and optimizing size by disabling PIE to
modify the defaults.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I8e67a9210e907e266ff6a78ba4d02e3259bb2b21
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Lets cast our macros to the right types and reduce a few MISRA
warnings.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I0dc06072713fe7c9440eca0635094c5f3ceb7f1c
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We compute BL31_END - BL31_START on the fly, which is basically
BL31_SIZE. Lets just use the BL31_SIZE directly so that we dont
complicate PIE relocations when actual address is +ve and -ve offsets
relative to link address.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I5e14906381d2d059163800d39798eb39c42da4ec
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Since we are using static xlat tables, we need to account for exact
count of table entries we are actually using.
peripherals usart, gic, gtc, sec_proxy_rt, scfg and data account for 6 entries
and are constant, however, we also need to account for:
bl31 full range, codebase, ro_data as additional 3 region
With USE_COHERENT_MEM we do add in 1 extra region as well.
This implies that we will have upto 9 or 10 regions based on
USE_COHERENT_MEM usage. Vs we currently define 8 regions.
This gets exposed with DEBUG=1 and assert checks trigger, which for some
reason completely escaped testing previously.
ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:97
BACKTRACE: START: assert
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I962cdfc779b4eb3b914fe1c46023d50bc289e6bc
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We actually have additional table entries than what we accounted for in
our size. MAX_XLAT_TABLES is 8, but really we could be using upto 10
depending on the platform. So, we need an extra 8K space in.
This gets exposed with DEBUG=1 and assert checks trigger, which for some
reason completely escaped testing previously.
ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:97
BACKTRACE: START: assert
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I5c5d04440ef1fccfaf2317066f3abbc0ec645903
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This allows the the Matterhorn ELP Arm core to operate at its
designated OPP.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I7ccef0cfd079d630c3cfe7874590bf42789a1dca
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PSA wording is not longer associated with FF-A.
Change-Id: Id7c53b9c6c8f383543f6a32a15eb15b7749d8658
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
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