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* Merge "docs: update TZC secured DRAM map for FVP and Juno" into integrationMadhukar Pappireddy2023-05-091-4/+34
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| * docs: update TZC secured DRAM map for FVP and JunoManish V Badarkhe2023-05-081-4/+34
| | | | | | | | | | | | | | | | Updated the documentation to include missing details about the TZC secured DRAM mapping for the FVP and Juno platforms. Change-Id: I10e59b9f9686fa2fef97f89864ebc272b10e5c0b Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | Merge changes I06b35f11,If80573d6 into integrationManish Pandey2023-05-094-171/+1
|\ \ | | | | | | | | | | | | | | | * changes: docs: remove plat_convert_pk() interface from release doc chore(io): remove io_dummy driver
| * | docs: remove plat_convert_pk() interface from release docSandrine Bailleux2023-04-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The code was already removed as part of commit 4ac5b3949d87 "refactor(auth): replace plat_convert_pk". The present commit just removes it from the release documentation. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I06b35f110c844267d69a865df55dd451ed2f08cd
| * | chore(io): remove io_dummy driverSandrine Bailleux2023-04-284-170/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In accordance with [1], delete the io_dummy driver code in preparation for the v2.9 release. [1] https://trustedfirmware-a.readthedocs.io/en/latest/about/release-information.html Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: If80573d6f889624ef06b099fd267ee85f3a6331e
* | | Merge "feat(mt8188): add MT8188 SPM debug logs" into integrationManish Pandey2023-05-098-11/+86
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| * | | feat(mt8188): add MT8188 SPM debug logsJason Chen2023-05-088-11/+86
| | |/ | |/| | | | | | | | | | | | | | | | Add debug logs for tracking the status of suspend and resume. Change-Id: Id2d2ab06fadb3118ab66f816937e0dd6e43dbdc3 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
* | | Merge changes from topic "assert_boolean_set" into integrationManish Pandey2023-05-096-17/+15
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: build!: check boolean flags are not empty fix(build): add a default value for INVERTED_MEMMAP fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOG fix(st-crypto): move flag control into source code fix(stm32mp1): always define PKA algos flags fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF
| * | | build!: check boolean flags are not emptyYann Gautier2023-05-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For numeric flags, there is a check for the value to be set. Do the same for boolean flags. This avoids issues where a flag is defined but without a value, leading to potential unexpected behaviors. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: Ib00da2784339471058887e93434d96ccba2aebb2
| * | | fix(build): add a default value for INVERTED_MEMMAPYann Gautier2023-05-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is needed to check the validity of boolean flags with the updated macro assert_boolean. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I185beb55606a4ca435d2fee2092fc61725859aa1
| * | | fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOGManish Pandey2023-05-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With introduction of check on boolean flags, it should be ensured that each boolean flag has default value provided by platform. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ia92c3dded842e14099b4a7667569605d7066a8f9
| * | | fix(st-crypto): move flag control into source codeLionel Debieve2023-05-032-15/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the control from the include file to avoid compilation issue. Add the check in the source code instead. Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com> Change-Id: I533f829607f76389399a3e8dbc3c6095278562ab
| * | | fix(stm32mp1): always define PKA algos flagsYann Gautier2023-05-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flags to set PKA algo are set to 0 when TRUSTED_BOARD_BOOT is not set. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Ib70a2bc51451a2047d7a50a8307e9063d4a2a0ee
| * | | fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEFYann Gautier2023-05-031-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag just needs to be defined, and does not need to have a boolean value. Remove it from the assert_booleans check. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I4e4c9ae1e5003ca2cf7c0c0e31d1561d032937c8
* | | | Merge changes from topics "gr/gcc12", "jc/toolchain_update_2.9" into integrationManish Pandey2023-05-093-1/+11
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(build): update GCC to 12.2.Rel1 version fix(build): allow lower address access with gcc-12
| * | | | docs(build): update GCC to 12.2.Rel1 versionJayanth Dodderi Chidanand2023-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating toolchain to the latest production release version 12.2.Rel1 publicly available on https://developer.arm.com/ We build TF-A in CI using: AArch32 bare-metal target (arm-none-eabi) AArch64 ELF bare-metal target (aarch64-none-elf) Change-Id: Ib603cf7417e6878683a1100d5f55311188e36e8e Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
| * | | | fix(build): allow lower address access with gcc-12Govindraj Raja2023-05-092-0/+10
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With gcc-12 any lower address access can trigger a warning/error this would be useful in other parts of system but in TF-A there are various reasons to access to the lower address ranges, example using mmio_read_*/writes_* So setup to allow access to lower addresses while using gcc-12 Change-Id: Id1b4012b13bc6876d83b90a347fee12478a1921d Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | | | Merge "feat(fvp): introduce PLATFORM_TEST_RAS_FFH config" into integrationManish Pandey2023-05-093-3/+72
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| * | | feat(fvp): introduce PLATFORM_TEST_RAS_FFH configManish Pandey2023-05-043-3/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While doing RAS related tests there were few patches related with fault injection and handling were applied through CI hooks. These patches were invisible as they were applied and removed after the build is done. This patch introduces build macro PLATFORM_TEST_RAS_FFH and moves the patches applied through CI under this. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Iddba52f3ebf21f575a473e50c607a944391156b9
* | | | Merge changes from topic "mp/group0_support" into integrationManish Pandey2023-05-0410-16/+82
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * changes: feat(tc): allow secure watchdog timer to trigger periodically feat(sbsa): helper api for refreshing watchdog timer
| * | | | feat(tc): allow secure watchdog timer to trigger periodicallyMadhukar Pappireddy2023-05-047-13/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: 1. Configures SBSA secure watchdog timer as Group0 interrupt for TC platform while keeping it as Group1 secure interrupt for other CSS based SoCs. 2. Programs the watchdog timer to trigger periodically 3. Provides a Group0 interrupt handler for TC platform port to deactivate the EL3 interrupt due to expiry of secure watchdog timer and refresh it explicitly. Change-Id: I3847d6eb7347c6ea0e527b97b096119ca1e6701b Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | | | feat(sbsa): helper api for refreshing watchdog timerMadhukar Pappireddy2023-05-043-3/+18
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a helper API to explicitly refresh SBSA secure watchdog timer. Please refer section A.3 of the following spec: https://developer.arm.com/documentation/den0029/latest/ Change-Id: I2d0943792aea0092bee1e51d74b908348587e66b Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | | Merge "feat(fvp): define ns memory in the SPMC manifest" into integrationMadhukar Pappireddy2023-05-042-9/+24
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| * | | | feat(fvp): define ns memory in the SPMC manifestJ-Alves2023-05-032-9/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPMC (Hafnium) looks for secure and non-secure ranges in its manifest. Those relate with ranges that can be used by SPs in their FF-A manifests. The NS memory that is not used by SPs will be assigned to the NWd, for it to share memory with SPs as needed. Thus, this limits the memory the NWd can share with SPs, to prevent NWD VMs from sharing memory that belongs to other critical components. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Iad03eb138a57068fbb18c53141bdf6bf9c171b28
* | | | | Merge changes from topic "allwinner_t507" into integrationMadhukar Pappireddy2023-05-0413-129/+187
|\ \ \ \ \ | |_|/ / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: feat(allwinner): add support for Allwinner T507 SoC feat(allwinner): add function to detect H616 die variant feat(allwinner): add extra CPU control registers refactor(allwinner): consolidate sunxi_cfg.h files
| * | | | feat(allwinner): add support for Allwinner T507 SoCMikhail Kalashnikov2023-04-263-30/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner T507 SoC is using the same die as the H616, but in a different package. On top of this, there is at least one different die revision out there, which uses a different CPU cluster control block. The same die revision has been spotted in some, but not all, H313 SoCs. Apart from that IP block, the rest of the SoC seems the same, so we can support them using the existing H616 port. The die revision can be auto-detected, so there is no extra build option or knowledge needed. Provide the deviating CPU power up/down sequence for the die variant. The new IP block uses per-core instead of per-cluster registers, but follows the same pattern otherwise. Since the CPU ops code is shared among all Allwinner SoCs, we need to dummy-define the new register names for the older SoCs. The actual new code is guarded by a predicate function, that is hard coded to return true on the other SoCs. Since this is a static inline function in a header file, the compiler will optimise away the unneeded branch there, so the generated code for the other SoCs stays the same. Change-Id: Ib5ade99d34b4ccb161ccde0e34f280ca6bd16ecd Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | feat(allwinner): add function to detect H616 die variantAndre Przywara2023-04-266-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner provides a number of SoCs that use the same die as the H616. Some of those chips apparently use a slight variation of that die, that differs in the way the CPU cores' power and reset controls are handled. This die variation can be detected by reading the SRAM version register. Provide a predicate function that returns false if that die variant is used. Since the CPU power control code is shared for all supported SoCs, we provide an instance of this function for each SoC, as a static inline, and return true on all other SoCs. This allows to always use this function, and still let the compiler optimise away the unneeded branch for those older SoCs. This function is unused for now, but is needed in the next patch. Change-Id: I49e014b895b7e2f55b4e7dc2b3d8aa31cee711b5 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | feat(allwinner): add extra CPU control registersMikhail Kalashnikov2023-04-263-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The die used in several variants of the Allwinner H616 SoC (H313, T507) seems to produced in at least two revisions. The newer one differs from the original by using a different CPU control register IP block. Add those newly used register offsets to the respective header file. The MMIO block itself is actually present in both variants, though the registers are different. The new registers tend to use one register per core, in contrast to one register per cluster in the older revisions. Change-Id: Ifbda1bdc67a6a16fbb901dbc83996e4a148b7602 Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | refactor(allwinner): consolidate sunxi_cfg.h filesAndre Przywara2023-04-265-101/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The header files describing the CPU cluster configuration IP block for the H6 and H616 are actually identical, so merge them into one file and move that to a common location. There is an upcoming SoC which will similarly share a header file with the R329 SoC, so move that to the same location already. In Allwinner's BSP source those two SoC groups are typically called "NCAT" and "NCAT2", so use those names for the shared header files. No functional change. Change-Id: I98318373577344dbe228a81fa331ce660df32b5f Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | | Merge "fix(tc): only suspend booting after running plat tests" into integrationSandrine Bailleux2023-05-041-1/+3
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| * | | | | fix(tc): only suspend booting after running plat testslaurenw-arm2023-05-041-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. When doing a normal boot, tc_bl31_common_platform_setup() should simply configure the platform and return. 2. When we are running the platform tests instead, tc_bl31_common_platform_setup() should run the tests then suspend booting (and thus never return). We were incorreclty suspending the boot in case 1 as well. Put that code under a preprocessor condition (PLATFORM_TEST_NV_COUNTERS or PLATFORM_TEST_TFM_TESTSUITE) to fix this. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I7d20800e3bcd85261e2cdad325586d184e12a3e3
* | | | | | Merge changes from topic "mp/group0_support" into integrationOlivier Deprez2023-05-0311-6/+189
|\ \ \ \ \ \ | |/ / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(spm): support for handling Group0 interrupts feat(spmd): introduce platform handler for Group0 interrupt feat(spmd): add support for FFA_EL3_INTR_HANDLE_32 ABI feat(spmd): register handler for group0 interrupt from NWd
| * | | | | docs(spm): support for handling Group0 interruptsMadhukar Pappireddy2023-05-011-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Please refer the doc update. Change-Id: Ib79fae1296bc28fa9bd0cd79609d6153bb57519b Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | | | | feat(spmd): introduce platform handler for Group0 interruptMadhukar Pappireddy2023-05-018-3/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a handler for FVP platform to triage Group0 secure interrupts. Currently, it is empty but serves as a placeholder for future Group0 interrupt sources. Moreover, this patch also provides a dummy implementation of the above mentioned platform hook for QEMU, corstone100, n1sdp and hikey960 ports. Change-Id: I01d3451408f47ac313b0af74046cce89f89b85bb Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | | | | feat(spmd): add support for FFA_EL3_INTR_HANDLE_32 ABIMadhukar Pappireddy2023-05-012-2/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When Group0 Secure interrupts in secure world get trapped to S-EL2 SPMC, FFA_EL3_INTR_HANDLE ABI is invoked by SPMC to delegate interrupt handling to EL3 firmware (i.e., SPMD). SPMD further delegates to platform handler which successfully handles the Group0 secure interrupt before returning control to SPMC. Change-Id: I8cc0fec20803b96c81582910ad2668e38b167fb8 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | | | | feat(spmd): register handler for group0 interrupt from NWdMadhukar Pappireddy2023-05-011-0/+43
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPMD registers a generic handler with the interrupt management framework to handle Group0 secure interrupt from normal world. The handler further delegates to the platform for successful handling of the interrupt. Change-Id: I9cdc721810b09e01190cdcab42c50830792a26e2 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | | | Merge changes I92826714,I9431f9d1 into integrationManish Pandey2023-05-033-4/+13
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: build(psci): move `runtime_errata.S` to PSCI build: allow BL-specific includes/definitions
| * | | | | build(psci): move `runtime_errata.S` to PSCIChris Kay2023-05-032-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the runtime errata source file into the PSCI library, as PSCI is the only component directly dependent on it, and it doesn't require internal access to the CPUs library. Change-Id: I92826714d49b1b0131f62c158543b4c167ab9aa8 Signed-off-by: Chris Kay <chris.kay@arm.com>
| * | | | | build: allow BL-specific includes/definitionsChris Kay2023-05-031-3/+12
|/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change introduces the `BLx_INCLUDE_DIRS` and `BLx_DEFINES` Makefile variables, which can be used to append include directories and preprocessor definitions to specific images created using the `MAKE_BL` Makefile macro. Change-Id: I9431f9d1cbde5b0b2624d9ce128a4f043c74c87f Signed-off-by: Chris Kay <chris.kay@arm.com>
* | | | | Merge changes I9d06e0ee,I6980e84f into integrationManish Pandey2023-05-0310-7/+100
|\ \ \ \ \ | |_|_|/ / |/| | | | | | | | | | | | | | | | | | | * changes: feat(tegra): implement 'pwr_domain_off_early' handler feat(psci): introduce 'pwr_domain_off_early' hook
| * | | | feat(tegra): implement 'pwr_domain_off_early' handlerVarun Wadekar2023-04-267-7/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the pwr_domain_off_early handler for Tegra platforms. Powering off the boot core on some Tegra platforms is not allowed and the SOC specific helper functions for Tegra194, Tegra210 and Tegra186 implement this restriction. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I9d06e0eee12314764adb0422e023a5bec6ed9c1e
| * | | | feat(psci): introduce 'pwr_domain_off_early' hookVarun Wadekar2023-04-263-0/+32
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the 'pwr_domain_off_early' hook for platforms wanting to perform housekeeping steps before the PSCI framework starts the CPU power off sequence. Platforms might also want to use ths opportunity to ensure that the CPU off sequence can proceed. The PSCI framework expects a return code of PSCI_E_DENIED, if the platform wants to halt the CPU off sequence. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I6980e84fc4d6cb80537a178d0d3d26fb28a13853
* | | | Merge "feat(xilinx): sync copyright format" into integrationJoanna Farley2023-05-0213-14/+14
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| * | | | feat(xilinx): sync copyright formatMichal Simek2023-04-2613-14/+14
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | Use the same format in all files 's/Copyright (C)/Copyright (c)/g'. Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7 Signed-off-by: Michal Simek <michal.simek@amd.com>
* | | | Merge "refactor(cpus): use BIT macro in a consistent manner" into integrationBipin Ravi2023-05-021-3/+3
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| * | | | refactor(cpus): use BIT macro in a consistent mannerOkash Khawaja2023-04-281-3/+3
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In assembly code, BIT macro is used with a preceding hash #. Let's update Cortex X1 code to follow the same convention. Excluding hash doesn't cause compilation to fail or emit incorrect code. Signed-off-by: Okash Khawaja <okash@google.com> Change-Id: If304cdf90542d2edcab3e2d66cd7e905ff7fd047
* | | | Merge "feat(el3-runtime): handle traps for IMPDEF registers accesses" into ↵Manish Pandey2023-05-026-5/+56
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| * | | | feat(el3-runtime): handle traps for IMPDEF registers accessesVarun Wadekar2023-04-306-5/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces support to handle traps from lower ELs for IMPDEF system register accesses. The actual support is left to the platforms to implement. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I623d5c432b4ce4328b68f238c15b1c83df97c1e5
* | | | | Merge "build: deprecate Arm rde1edge" into integrationManish V Badarkhe2023-05-022-2/+7
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| * | | | | build: deprecate Arm rde1edgeManish V Badarkhe2023-04-202-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arm has decided to deprecate the rde1edge platform. The development of software and fast model for this platform have been discontinued. Hence, updated the makefile to warn about the deprecation of this platform, and also reflected it in the documentation. Change-Id: I0d44de4590dd5dce02c7c4b433df25dc438e6c49 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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