From 10d5cf1b26f03d61a90cdcff5163965fa48e291c Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Thu, 1 Sep 2022 11:02:59 -0500 Subject: feat(ti): disable L2 dataless UniqueClean evictions Do this early before we enable caching as a workaround for ARM A72 Errata #854172. Signed-off-by: Andrew Davis Change-Id: Ic878fdb49e598da0ea6ade012712f8f57023678e --- plat/ti/k3/common/k3_helpers.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'plat/ti') diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S index 6742e74f1..da94c1644 100644 --- a/plat/ti/k3/common/k3_helpers.S +++ b/plat/ti/k3/common/k3_helpers.S @@ -118,6 +118,12 @@ a72: orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE msr CORTEX_A72_L2CTLR_EL1, x0 + + mrs x0, CORTEX_A72_L2ACTLR_EL1 + /* Enable L2 UniqueClean evictions with data */ + orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN + msr CORTEX_A72_L2ACTLR_EL1, x0 + isb ret endfunc plat_reset_handler -- cgit v1.2.1