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* nb/intel/snb: Remove stale systemagent aka. mrc binariesNico Huber2019-03-052-0/+0
| | | | | | | | The remaining `systemagent-r6` is the only one compatible to the current coreboot code and supports both Sandy and Ivy Bridge. Change-Id: I1bddaf0e403cdc2f64124ed4a7da0c4ffcbe47a3 Signed-off-by: Nico Huber <nico.h@gmx.de>
* soc/amd/stoneyridge/PSP: Update SMU firmwareRichard Spiegel2018-12-075-1/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | - [Customer] [FIX] Fix UVD PG Tile power on/off issue, ticket#119099882. - PLAT-20827 workaround,added flag to bypass guard of SMU then force NBPstate as expected for HP diag program. - PLAT-20827 WA, added flag to bypass guard of SMU then force NBPstate as expected for HP diag program at specific bootup duration. - PLAT-20827,WA, added isWAByPass flag to bypass guard checking of SMU thus NBPstate can be forced before NBDpm enabled. - PLAT-20827,WA,added 2 messages(0x89,0x90) for customer let them can run their own diag program with NBPstate-Forced - PLAT-20827,WA, added msg(0x89,0x90) to bypass guard checking of SMU then force NBPstate as expected for HP diag program. - Reversing sanity check for Min and Max Nclk levels. - [Customer] [WA] Force Unbwake in unb.c to workaround Chromebook issue. - [IMP] Add FWHeader for STN Kicker, CTS Fix. - [WKA] Apply a dummy vid change on VddNb to ensure PSI0. - [Customer] [WA] Modify ForceUnbWake to original method per farm testing results. BUG=b:119099882 TEST=Build and boot grunt. Run suspend_stress_test. Change-Id: I9b003cedd42dd77be813e33a219d5029fca772d2 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* cpu/intel: Run microcode update scriptNico Huber2018-12-0633-101/+29
| | | | | | | | | `model_6xx` contained a microcode update for 660 so that's moved to `model_66x`. `model_406fx` vanished, but it wasn't hooked up in core- boot so remove it. Change-Id: I03af43776d1a71a3c2d39b30a256c9f8058bfda1 Signed-off-by: Nico Huber <nico.h@gmx.de>
* cpu/intel: Remove microcode header files, we use binaries nowNico Huber2018-12-06141-30039/+0
| | | | | | | If somebody misses them, they are in the history. Change-Id: I560f85ff6b215d7785ac5346c45f4992cd93c18b Signed-off-by: Nico Huber <nico.h@gmx.de>
* Kahlee/liara: Update video BIOS to customize release binaryRichard Spiegel2018-12-052-0/+6
| | | | | | | | | | | | | | Liara Chromebook Stoney VBIOS BRT39865 BRT39865.001 12/05/18,01:13:54 CL#1716128 @ 15.49.0.18 ATOMBuild#436504 Major Changes included: 1. First Stoney VBIOS released to Liara update eDP power up sequence. BUG=b:120534087 TEST=Build liara, booted, tested eDP test compliance. Change-Id: I5a09cb5f3dc37b7920f79f04f54f272f1ff2bba2 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* Kahlee/aleena: Update video BIOS to customize release binaryRichard Spiegel2018-11-272-0/+14
| | | | | | | | | | | | | | | | 1. Change register UNIPHY_TMDP_REG3_TMDP_EDP_HIGH_VDIFF_CLK2_AND_PL0_VL0_VAL to 0x250d8001 2. Change register UNIPHY_TX_CONTROL3_TMDP_EDP_HIGH_VDIFF_CLK2_AND_PL0_VL0_VAL to 0x09000000 BUG=b:112618193 TEST=Build aleena, booted, tested eDP test compliance. Uploaded-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Change-Id: I171ad02d420922d36c15792a5da65680f350c225 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
* Grunt: Update video BIOS to production release binaryMartin Roth2018-10-292-2/+14
| | | | | | | | | | | | | Production release binary - 113-C91400-010 - version 015.049.000.018 Settings: - eDP HBR:Pre-emphasis increment=1,Swing increment = 8; - DP RBR/HBR:Pre-emphasis increment=3,Swing increment = 1; BUG=b:118509612 TEST=Build grunt & boot Change-Id: I79ad0ea5f0be8a1efaab0e3f85b3cad72452a861 Signed-off-by: Martin Roth <martinroth@chromium.org>
* soc/intel/quark: Add prebuilt QuarkFsp 2.0 binariesPatrick Georgi2018-10-1128-0/+1315
| | | | | | | | | | | | These are provided for convenience and to improve test coverage of our Quark based board builds. The binaries themselves aren't tested at all, but they're real builds: they may work, or they might kill a kitten every time you try to run them. If in doubt, build yourself: I added instructions. Change-Id: Id2e1a7574437d9f244e3a82c2e48e9645a8805e3 Signed-off-by: Patrick Georgi <pgeorgi@google.com>
* soc: Add BL31 for Cavium CN81xx SocPatrick Rudolph2018-07-264-0/+44
| | | | | | | | | | | | | * Add BL31.elf compiled using coreboot toolchain * Add README, LICENSE and VERSION * ATF Version 1.5 * Based on commit d48f193d11b4d4dca2675646ad76147f2d4765f2 * https://github.com/9elements/arm-trusted-firmware/commits/coreboot_bl31_blob * Added here as blob as code is not upstream * Can be removed as soon as it's upstream Change-Id: I99128cd05735c6dc429d51d642d6afe3f513be3e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* mainboard/google: Add folder kahlee for video binaryRichard Spiegel2018-07-243-0/+296
| | | | | | | | | | | | | The careena board needs different video setting to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, kahlee folder needs to be created and populated with modified VBIOS, release notes for modified VBIOS and license. BUG=b:111673328 TEST=none. Change-Id: I5c37a084340085e371c798a3b0e8dc5bd2adc769 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* Stoney Ridge: PSP bootloader updateKerry Brown2018-07-132-250/+248
| | | | | | | | | | | | The standard PSP bootloader firmware has assumptions regarding security processes which are not compatible with vboot functionality. This version is fully compatible with vboot. BUG=b:76202697 TEST=Runs on Grunt Change-Id: I2b8dd854f62990fa4829de45b4106773ef9b8cee Signed-off-by: Kerry Brown <kerry.brown@silverbackltd.com>
* cpu/intel: remove microcode header files for model_306axMartin Kepplinger2018-07-062-869/+0
| | | | | | | | | | | | | | | | coreboot doesn't use the microcode header files anymore. The binaries are included, see src/cpu/intel/*/Makefile.inc. In the past, Intel has released its microcode updates in said header file format, has later released both the headers and binaries, and now releases the binaries only. Headers and the scripts that take them in order to generate binaries will become obsolete in the future. This removes the microcode header files for model_306ax so that they don't get out of sync when a new microcode update binary is included. Change-Id: I92bf7020cce3e36e1e6bd0068553647f0ff78dbf Signed-off-by: Martin Kepplinger <martink@posteo.de>
* cpu/amd/family_15h: Add latest AMD ucode filePaul Menzel2018-06-281-0/+0
| | | | | | | | | | | | | | | | | | Add the updated microcode update files from the Linux firmware repository [1]. Since the last upload, the commits below were added to the Linux firmware repository. * 5f8ca0c linux-firmware: Update AMD microcode patch firmware * 7710151 linux-firmware: Update AMD cpu microcode * 7518922 Update AMD cpu microcode for family 15h The current microcode patches should have features helping to mitigate the Spectre vulnerabilities. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/amd-ucode Change-Id: I579abae1455a72007fc5931770b727e80b0b5b16 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
* pcengines/apu2: Disable ECC Exclusion rangeKyösti Mälkki2018-05-211-0/+0
| | | | | | | | | | | Address BUG465142: ECC error injection fails Do not set bit 0, EccExclEn, in register D18F5x240 as 1. Range was incorrectly enabled to cover all memory for cases without UMA (no integrated graphics). Change-Id: I34e551f739e29c26efc33b6774d7a6b4ee60ab6c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* cpu/intel: microcode: add license agreementMartin Kepplinger2018-05-141-0/+109
| | | | | | | | This adds the license Intel publishes these updates under. Source: https://downloadcenter.intel.com/download/27591 Change-Id: I4907aa59c3e9a82b9e3ce96cfe733b74e5a8d4b0 Signed-off-by: Martin Kepplinger <martink@posteo.de>
* cpu/intel: add microcode updates 20180312 for new CPU modelsMartin Kepplinger2018-04-1931-783/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel's microcode release 20180312 includes updates for many more CPU models than we currently track. By looking at what is included, we create the missing directories and run the update-microcode.sh and microcode2bin.sh scripts. This is the resulting change. Header files are left out because they are not used anymore. Sidenote: Since we create model_6ax, the relevant files from model_6xx move to model_6ax. Everything else is trivial addition. The available release notes for this and preceding releases follow quoted here: 20180312 Release == Updates upon 20171117 release == MODEL STEP f-mm-s:pf version -- New Platforms -- BDX-DE EGW A0 6-56-5:10 e000009 SKX B1 6-55-3:97 1000140 -- Updates -- SNB D2 6-2a-7:12 29->2d JKT C1 6-2d-6:6d 619->61c JKT C2 6-2d-7:6d 710->713 IVB E2 6-3a-9:12 1c->1f IVT C0 6-3e-4:ed 428->42c IVT D1 6-3e-7:ed 70d->713 HSW Cx/Dx 6-3c-3:32 22->24 HSW-ULT Cx/Dx 6-45-1:72 20->23 CRW Cx 6-46-1:32 17->19 HSX C0 6-3f-2:6f 3a->3c HSX-EX E0 6-3f-4:80 0f->11 BDW-U/Y E/F 6-3d-4:c0 25->2a BDW-H E/G 6-47-1:22 17->1d BDX-DE V0/V1 6-56-2:10 0f->15 BDW-DE V2 6-56-3:10 700000d->7000012 BDW-DE Y0 6-56-4:10 f00000a->f000011 SKL-U/Y D0 6-4e-3:c0 ba->c2 SKL R0 6-5e-3:36 ba->c2 KBL-U/Y H0 6-8e-9:c0 62->84 KBL B0 6-9e-9:2a 5e->84 CFL D0 6-8e-a:c0 70->84 CFL U0 6-9e-a:22 70->84 CFL B0 6-9e-b:02 72->84 SKX H0 6-55-4:b7 2000035->2000043 20171117 Release -- New Platforms -- CFL U0 (06-9e-0a:22) 70 CFL B0 (06-9e-0b:2) 72 SKX H0 (06-55-04:b7) 2000035 GLK B0 (06-7a-01:1) 1e APL Bx (06-5c-09:3) 2c -- Updates -- KBL Y0 (06-8e-0a:c0) 66->70 -- Removed files -- SKX H0 (06-55-04:97) 2000022 20170511 Release -- Updates -- BDX-ML B0/M0/R0 (06-4f-01:ef) b00001f->b000021 Skylake D0 (06-4e-03:c0) 9e->ba Broadwell ULT/ULX E/F-step (06-3d-04:c0) 24->25 ULT Cx/Dx (06-45-01:72) 1f->20 Crystalwell Cx (06-46-01:32) 16->17 Broadwell Halo E/G-step (06-47-01:22) 16->17 HSX EX E0 (06-3f-04:80) d->f Skylake R0 (06-5e-03:36) 9e->ba Haswell Cx/Dx (06-3c-03:32) 20->22 HSX C0 (06-3f-02:6f) 39->3a 20170707 Release -- New Platforms -- KBL H0 (06-8e-09:c0) 62 KBL Y0 (06-8e-0a:c0) 66 KBL B0 (06-9e-09:2a) 5e SKX H0 (06-55-04:97) 2000022 Change-Id: Idd9252eef3202d84504c690e7348377254a7185e Signed-off-by: Martin Kepplinger <martink@posteo.de>
* cpu/intel: apply microcode updates 20180312 to currently tracked modelsMartin Kepplinger2018-03-2717-4178/+4563
| | | | | | | | | | | | | | | This updates Intel's microcode updates for the CPU models we currently track to the latest release. These include meltdown/spectre mitigations. Source: https://downloadcenter.intel.com/download/27591 Applying the scripts results in changes to the models with CPU ID 206ax, 306ax, 306cx and 4065x. I tested this on a Thinkpad X230 (model 306ax). The revision is then 1f instead of 1b; (dmesg|grep microcode); loaded by coreboot (not Linux). Change-Id: Idf5aa85681391707822bbfe493cff269ff2b88eb Tested-by: Martin Kepplinger <martink@posteo.de> Signed-off-by: Martin Kepplinger <martink@posteo.de>
* 3rdparty/blobs/pi/amd/00670F00/FT4: Release AGESA.binRichard Spiegel2018-03-132-0/+42
| | | | | | | | | | | | | | | | | Some fixes and improvements happened in AGESA that need to be ported to coreboot. Among them we have: 1) A fix to AGESA_ALERT (only shows up after fixing AGESA_WARNING) 2) A fix to resetting at AmdInitPost after a 0x0CF9 reset with 0x0E 3) A call out by the AP to do CAR teardown externally Commit new AGESA FT4 binary. BUG=b:70338633 COMMIT=3313d277 TEST=These fixes and improvements were tested on kahlee and grunt boards before committing to Google's repository. Change-Id: I030eb0c30f68c30435906cff8b68bc3e0469ba95 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* soc/amd/Stoneyridge: Update PSP binaries to AGESA 1.3.0.9Marc Jones2018-02-0112-13/+703
| | | | | | | | | | Update the PSP and SMU firmware files that accompany AGESA 1.3.0.9. BUG=b:69807482 TEST=build and boot Grunt Change-Id: I4be0af113bc4099329e57a0c287f473ef9714604 Signed-off-by: Marc Jones <marcj303@gmail.com>
* pi/amd/00670F00: Update AGESA to 1.3.0.9Marc Jones2018-02-014-0/+760
| | | | | | | | | | | | | | | Updates to 1.3.0.9 with the additional changes: Set BLDOPT_ALLOW_SPI_INTERFACE_UPDATE to FALSE Remove programming of WideIO0 Set FCH_NO_IR_SUPPORT for FT4 FAMILY15H_ST Fix SpreadSpectrum programming BUG:b:69807482 TEST=Build and boot Grunt Change-Id: I3de49438f72eadaddf40a0a2bf549c3404c7d1ff Signed-off-by: Marc Jones <marcj303@gmail.com>
* Kahlee/Grunt: Move remaining stoneyridge blobsRichard Spiegel2018-01-043-0/+0
| | | | | | | | | | | | | Rename northbridge/amd/00670F00/license.txt to northbridge/amd/00670F00/vbios_license.txt (to avoid conflict with another file license.txt already present in soc/amd/stoneyridge), then move northbridge/amd/00670F00/* into soc/amd/stoneyridge. BUG=b:70785272 TEST=none, just a move. Change-Id: I1481814e249d5daab4d6ed6c0964bf575b426bf5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* 3rdparty/blobs/soc/amd: Create stoneyridgeRichard Spiegel2017-12-1823-0/+1949
| | | | | | | | | | | | | | | | The organization of 3rdparty/blobs/southbridge/amd assumes supported features by codename. This will shortly cause problems as we deviate from the normal released functionality. Create new folder soc/amd/stoneyridge and move stoneyridge contents from southbridge/amd/kern folder into this new folder. This will permit later Stoneyridge specific changes to be separated from Carrizo. BUG=b:69613465 TEST=None. Change-Id: I1b76a6e6c4127ad13c608f392d619109d877914c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* amd/pi/00670F00: Update AGESA.binMarc Jones2017-06-212-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | This update consists of two changes. Stoney: Enable Boottime Calibration The BTC feature is required for the SMU to correctly support AVFS. Without it, the SMU may send unsupportable VIDs to the regulator and cause the system to crash. Stoney: Remove SERIRQ setup Remove the SERIRQ setup in AGESA. It is platform specific and there isn't an AGESA API for changing the setting. In addition to not having an override, it was being set in amd_init_post, prior to memory setup, so prior to any possible interrupt handler. Finally it was setting quiet mode, which isn't supported by some LPC devices that can't recover, once switched to continiuos mode. A corresponding change to hudson lpc setup code in coreboot is required. Change-Id: I66bc60957af88ce4604de0b3727ef77891beadfb Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* pi/00670F00: Add SMU firmware for Stoney fanless partsMarshall Dawson2017-03-252-0/+0
| | | | | | | | | Add additional firmware blobs from the PI package to be used with APU that are fused as "fanless" OPNs. Change-Id: I4bc965e6c66198ee3051a77d7c6f1ef0dc9433bc Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit cd1cde22ed50527c323f0b908b3541020adfa4ad)
* pi/00670F00: Correct license fileMarshall Dawson2017-03-252-366/+404
| | | | | | | | Adjust the wording from a stale license agreement to a new and improved version from AMD. Change-Id: Id713a932ff0b253142315fd66f5f039f696c6ddc Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* pi/00670F00: Add FT4 AGESA.bin for Stoney platformMarshall Dawson2017-03-253-0/+1172
| | | | | | | | | | Add the FT4 version of the Stoney binary PI which corresponds to the same revision level as the FP4 one. This was built from commit c14ef54a. Change-Id: Ifb41e03ebf64b22ef0de6a9d12943cc9df9ee1f8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 6b23fa8d79b0bcfea94bc6b723aafa36bc26e477)
* pi/00670F00: Add AGESA.bin for Stoney platformMarshall Dawson2016-12-153-0/+1172
| | | | | | | | | | Add a custom build to support Family 15h Models 70h-7Fh. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry pick from e6e15473efa0a8870306745cac334b335778bc64) Change-Id: Icf20543a3625fde83f78adef47a5d0ef0244515a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* pi/kern: Add blobs for Stoney platformMarshall Dawson2016-12-1415-0/+342
| | | | | | | | | | | Copy PSP blobs, keys, etc. from the PI 1.3.0.3 package. This supports Family 15h Models 70h-7Fh. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry pick from commit e25a97d6d97afddcab356a506913d2549c8e9b34) Change-Id: I735e155a7d08dd3630a0f4707d87a024fb094f56 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* southbridge/amd: Fix license filesMarshall Dawson2016-12-144-56/+56
| | | | | | | | | Replace non-ASCII characters with good values. These had consisted of formatted single and double quotes. No content of the license agreement is modified. Change-Id: I73acf1b7e3ab8e12b7bf70e73b0ef09d17ff9323 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* pi/amd: Fix AGESA.bin license filesMarshall Dawson2016-12-143-42/+42
| | | | | | | | | | | | | Replace non-ASCII characters with good values. These had consisted of formatted single and double quotes. No content of the license agreement is modified. This patch does not include the file for Stoney Ridge (00670F00) as that one contains new language from AMD. The three files here are identical and have been copied over time. Change-Id: I60b81bac0b5f3f8836871cc5c17e425aabc923e0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* northbridge/amd: Fix vbios license filesMarshall Dawson2016-12-144-56/+56
| | | | | | | | | Replace non-ASCII characters with good values. These had consisted of formatted single and double quotes. No content of the license agreement is modified. Change-Id: Iba33c2b2aa77e6dd311c2f390107c1494d678cac Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* pi/00670f00: Add Stoney Ridge VBIOSMarshall Dawson2016-12-143-0/+298
| | | | | | | | | | | Copy the generic binary image 006 and release notes from the PI 1.3.0.3 package. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 4e6801c9a75d2b0303c68b91fe6205fb28f761a5) Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Id8d8212ff4ff6a768cbf2607189e7fc391ea737b
* nvidia/tegra132: Remove unused blobsMartin Roth2016-09-055-134/+0
| | | | | | | | | | The tegra 132 SOC support was removed from the coreboot codebase in commit 9ba06995 - soc/nvidia/tegra132: remove tegra132 support Remove the blobs since the chip is no longer used. Change-Id: Ic4ea493b2b5bb4e337ed617c647ad330b6b254ac Signed-off-by: Martin Roth <martinroth@chromium.org>
* mainboard/pcengines/apu2: Add AGESA binary.Philipp Deppenwiese2016-07-051-0/+0
| | | | | | | | Any later AGESA binaries does not work for this board because of commit 95b80508d9ba26350b7e699decd47074f480a2f2 in the blobs repo. Change-Id: I9eaf66d6c6a3af4cb9dce7d43152afe2111720d4 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
* qualcomm/ipq40xx: add more dummy filesPatrick Georgi2016-05-093-0/+2
| | | | | | | Again, these aren't the real thing. Change-Id: I0b51e7ee1a6f4e9b153c588ac9ef030226bba357 Signed-off-by: Patrick Georgi <pgeorgi@google.com>
* qualcomm/ipq40xx: Add placeholdersPatrick Georgi2016-05-094-0/+4
| | | | | | | | | These are dummy files. To build working images, you'll need to fetch the actual binaries from an existing image (or convince Qualcomm to give you the binaries). Change-Id: I89115b91bbe4c998c9b9854e6178e9788009b3a4 Signed-off-by: Patrick Georgi <pgeorgi@google.com>
* samsung/exynos5250: Add update-bl1.shStefan Reinauer2015-12-141-0/+26
| | | | | | | Moved from a lonely directory in the coreboot source tree Change-Id: I5312202d3068055e0297ddf5a9fa0672e9904c5a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Revert "Remove microcode stored in C-array format"Stefan Reinauer2015-11-27166-0/+54609
| | | | | | | | | | | | | | | This reverts commit 832bc6f1f8ffafc5ff397fd95616fdae988f224f. For compliance with our binary policy (*), and to be able to run the scripts producing the blobs without having to pull magic files from magic places, put these "source" files back in. (*) 2. Appropriate license (redistributable) a. The binary must be accompanied by a distribution license. [..] Change-Id: I99792dde209809ed8c90f5081593e38dc3b471b3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* binary policy: cosmetic cleanupStefan Reinauer2015-11-131-8/+9
| | | | | | | | - Add a title for 3. - Drop a. if there's no b. Change-Id: I672a685e1d7a5dff7f0723da6a8a935e9f9ed469 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* AMD Merlin Falcon: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5)WANG Siyuan2015-11-129-6/+10
| | | | | | | | | | Update AGESA.bin, PSP and VBIOS to CarrizoPI Version 1.1.0.1 Tested on Bettong rev C(DDR3) and rev F(DDR4). Both of the boards can boot to Windows 10. PCIe slots, USB and NIC work. Change-Id: Ie86bb0cf2e3cae7a9b446dfa93145ab2fce36c4f Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* blobs: Add Binary Policy documentMarc Jones2015-10-271-0/+60
| | | | | | | | | | | | While coreboot attempts to be binary free, some coreboot mainboards require vendor binaries to support silicon and features. It is an unfortunate fact, as silicon has become more complicated, vendors are using more binaries to support their silicon. This policy sets standards and expectations for vendor binaries. Change-Id: I284b713975ac9fc4d8a19f26d20e2223f4250cbd Signed-off-by: Marc Jones <marcj303@gmail.com>
* amd/model_10xxx: Upload latest AMD microcode files and remove unified blobTimothy Pearson2015-10-123-0/+0
| | | | | Change-Id: I80bdf5310801484f3ebf5b2343a69e780048bd0d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
* Remove microcode stored in C-array formatAlexandru Gagniuc2015-10-03166-54609/+0
| | | | | | | It's all binary now. Change-Id: I1dd897624b498e3707ac65f3cdcef7d857a1e6cf Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* soc/intel: Store microcode in binary formatAlexandru Gagniuc2015-09-242-0/+0
| | | | | Change-Id: I0020f3dc90e22d0ce443f7d4888272ac805ac84f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* cpu/amd/model_fxx: Store microcode in binary formatAlexandru Gagniuc2015-09-091-0/+0
| | | | | Change-Id: I1f7a67fd5801d96a70bf382cc8d76f3e121ea081 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* cpu/amd/model_10xxx: Store microcode in binary formatAlexandru Gagniuc2015-09-091-0/+0
| | | | | Change-Id: I0e8d675fcbd8fa281753fcc82543ec938d36dde7 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* cpu/via/nano: Store microcode in binary formatAlexandru Gagniuc2015-09-091-0/+0
| | | | | Change-Id: I7067e85d63f22de38d6f23430dd991698b15e763 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD Steppe Eagle: Update to MullinsPI 1.0.0.A (Binary PI 1.1)WANG Siyuan2015-08-259-10/+69
| | | | | | | | | | Update AGESA.bin and PSP to MullinsPI 1.0.0.A. This is tested on Olive Hill Plus. The board can boot to Windows 7. PCIe slot, USB and NIC work. Change-Id: I67817dc59f9984019ac66ce7a9ab1a2f34e0be9e Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)WANG Siyuan2015-08-1212-29/+66
| | | | | | | | | | Update AGESA.bin, PSP and VBIOS to CarrizoPI Version 1.1.0.0 Tested on Bettong rev C(DDR3) and rev F(DDR4). Both of the boards can boot to Windows 8.1. PCIe slots, USB and NIC work. Change-Id: Icb7a4f0724d9e18b22e8ffee13d19d20ddeb9dcb Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* pi: Move AMD sources from blobs to vendorcodeMarc Jones2015-08-07104-56785/+0
| | | | | | | | | The AMD AGESA binaryPI sources were incorrectly committed to 3rdparty/blobs. Move them from blobs to vendorcode. Commit this after the files are committed to coreboot vendorcode/. Change-Id: If583c15ba4f7d63df264e09573c2605824836da0 Signed-off-by: Marc Jones <marc.jones@se-eng.com>
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