summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
...
* soc/mediatek/mt8192: Update DRAM blob to 13869.0Yu-Ping Wu2021-04-094-5/+17
| | | | | | | | | | | | Update dram.elf from version 1.5.1 to 1.6.0, built from Chrome OS 13869.0.0. BUG=b:170687062 TEST=Hayato boots Cq-Depend: chromium:2783629, chromium:2783630 Change-Id: I13b63760448c1849ce73074bf1d0d6a118c336f8 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
* mb/google/guybrush: Update APCB to latest test buildMartin Roth2021-04-082-1/+4
| | | | | | | | - Fix UMAmode - Enable VBL/PSP to control eDP VDD. Change-Id: Ief5d7beaf54ff870eb79f20e39ee09cf857ec816 Signed-off-by: Martin Roth <martinroth@chromium.org>
* soc/mediatek/mt8183: Update DRAM calibration blob to 1.5.0Yu-Ping Wu2021-04-074-1/+17
| | | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.224.0, which contains the version number string. BUG=b:173653085 TEST=emerge-kukui coreboot TEST=Krane boots BRANCH=kukui Change-Id: Ic113a6346cb57186efad77e36cc99ec957765b0e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
* soc/mediatek/mt8183: Update DRAM calibration blob to 12573.197Hung-Te Lin2021-04-073-1/+9
| | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.197.0, supporting 8GB byte mode. BUG=None BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # boots properly Change-Id: Id445666d5f6a372f605eecf0f24b03ba1bf3efcc Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
* soc/mediatek/mt8183: Update DRAM calibration blob to 12573.136Hung-Te Lin2021-04-073-1/+8
| | | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.136.0, improve 8GB stability. BUG=None BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # boots properly Change-Id: Ie7baec46be614fb8bb942d49468de2d0ccd9e761 Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8183: Update DRAM calibration blob to 12573.132Hung-Te Lin2021-04-073-1/+9
| | | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.132.0, supporting 6GB/4GB memory modules. BUG=None BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # boots properly Change-Id: I4805e7c67cedfd90abe9f595487abe918f386011 Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8183: Update DRAM calibration blob to 12573.28Hung-Te Lin2021-04-073-1/+8
| | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.28.0. BUG=b:80501386 BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # boots properly Change-Id: I64987555f225a165d64003c1ccfb73da16c376b7 Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8183: Update DRAM calibration blob to 12573.25Hung-Te Lin2021-04-072-0/+7
| | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.25.0. BUG=b:80501386 BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # And boots properly Change-Id: Ia2d4571eb0a214989b31f87f3a6ecdcdc44cd37d Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8183: Update DRAM calibration blob to 12573.20Hung-Te Lin2021-04-073-1/+8
| | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.20.0. BUG=b:80501386 BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # And boots properly Change-Id: Idd889fd4383295a3568d63d7f6834bf52a7466d4 Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8183: Update DRAM full calibration blobHung-Te Lin2021-04-073-1/+9
| | | | | | | | | | | | | | A new release of dram.elf supporting dramc protocol version 2, built from Chrome OS 12573.16.0. BUG=b:80501386 BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # And boots properly Change-Id: I7db6da9acc52855697de76b112baecbdf842588a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8183: Add DRAM full calibration blobYu-Ping Wu2021-04-074-0/+118
| | | | | | | | | | | | | | | The dram.elf is added for mt8183 DRAM full calibration, which contains full calibrations for 3 frequencies: - 1600Mbps, 2400Mbps, 3200Mbps for discrete DDR, - 1600Mbps, 3200Mbps, 3600Mbps for eMCP DDR. BUG=b:80501386 BRANCH=kukui TEST=Full calibration runs successfully Change-Id: I5386af0e25878db40f013ef42df1f074426f13c2 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* mb/google/guybrush: Update APCB - disable debugMathew King2021-03-242-0/+4
| | | | | | | | BUG=b:182850520 TEST=Boot to coreboot without ABL debug Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ice39d9e62da95dceb7e038551a45616fdd2633d1
* mb/google/guybrush: Add APCB to get through memory trainingMathew King2021-03-182-0/+3
| | | | | | | | BUG=b:182850520 TEST=guybrush boots to coreboot Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Idf60ae8de584182d01397b60afe3a9a1e99106f3
* soc/mediatek/mt8192: Add EMI Settings of 8GB Normal ModeXi Chen2021-03-174-1/+20
| | | | | | | | | By default, 8GB DDRs may use byte mode, but some DDRs also use normal mode, add normal mode settings for supporting this kind of DDRs. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ia446c8d9279d815ff415af531a9bd872bded0515
* soc/mediatek/mt8192: Update MCUPM firmwareAndrew SH Cheng2021-03-174-2/+7
| | | | | | | | 1. Update mcupm.bin to v1.00.06 2. Modify SRAM layout for CPU DVFS Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com> Change-Id: Icfeb05de6a68379a17d6379e919c112dc8d8836f
* soc/mediatek/mt8192: Add version info for SSPMTinghan Shen2021-03-174-3/+8
| | | | | | | | 1. Label sspm.bin with version v1.0.0 2. disable boot log Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Change-Id: I23269e0ef69b988d10a467925111cc3e4ff76135
* mb/google/guybrush: Add initial APCBMartin Roth2021-03-122-0/+23
| | | | | | | | | | | | | | | | | | | | | This is the initial APCB generated for the guybrush platform. SPDs: 0: lp4x-spd-4.hex 1: lp4x-spd-1.hex 2: lp4x-spd-9.hex All other GPIO Settings are unused. The GPIOs to use for the SPD identifiers: Bit 0: GPIO 109 Bit 1: GPIO 87 Bit 2: GPIO 75 Bit 3: GPIO 88 BUG=b:182510885 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I01e9caf18735bec3858c5727ae2a4c999f1a2e87
* mb/amd/majolica: Update to use proper APCBs built for MajolicaMatt Papageorge2021-03-054-0/+0
| | | | | | | | | | | | | Some of the previous binaries were incorrect and should not be used for Majolica because they are templates instead of APCBs specifically built for the board. This APCB update also places the UMA region under 4G and size 32 MB which is essential for video output. TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory region size, base and alignment. Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Change-Id: I353f7b68a3279b8d1a46af5ae1095ad764d7f9c2
* mb/amd/bilby: Add APCB configuration fileRitul Guru2021-02-091-0/+0
| | | | | | | This will enable coreboot development on the Bilby reference board. Change-Id: I85a388289a8275ab18c0bed8ea9a637d4cd7c138 Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
* mb/amd/majolica: Add APCB configuration filesMarshall Dawson2021-01-163-0/+0
| | | | | | | | | Allow for Cezanne and Majolica development by adding initial APCB files. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Change-Id: Ifa93ae326545071a9a9c0f5a00cfc10e36c3a9a9
* soc/mediatek/mt8192: Support discrete DRAM modulesXi Chen2020-12-153-1/+9
| | | | | | | | | | | In additional to eMCP, some MT8192 devices may use discrete DRAM module and need a different calibration process. BUG=b:173653085 TEST=Stress pass Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ieddff1545de856f99c29cfe611bf6a5bd8deb0f3
* soc/mediatek/mt8192: Update MCUPM firmwareAndrew-sh.Cheng2020-12-153-1/+6
| | | | | | | | | | | 1. mcupm.bin version v1.0.5 2. Add EM table into mcupm 3. Add SVS CPU BUG=b:173653085 Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com> Change-Id: I7bd06f2b437b3ef0d3a076d8eef1cfc7ddb2c8e0
* soc/mediatek/mt8192: Add MCUPM firmwareCK Hu2020-12-154-0/+41
| | | | | | | | | | 1. mcupm.bin version v1.0.4 2. Add cpufreq opp table into mcupm BUG=b:173653085 Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com> Change-Id: I57b8b666cd7c6665c945589cc1d7f8a8129d0875
* soc/mediatek/mt8192: Add SSPM firmwareTingHan.Shen2020-12-154-0/+28
| | | | | | | | | Add sspm.bin to support suspend/resume. BUG=b:173653085 Signed-off-by: TingHan.Shen <tinghan.shen@mediatek.com> Change-Id: Ibd1088b7cdf747bc5b32aae6bf34db09207928bc
* soc/mediatek/mt8192: Support 26M clock off in SPMRoger Lu2020-12-153-1/+4
| | | | | | | | | | | SPM suspend can turn 26M clock off when system goes into suspend to save 138mW of power. BUG=b:173653085 TEST=Asurada system suspend/resume pass Change-Id: I5cf99cab59cfeaa7fd16fcf8ac274e4f530122d9 Signed-off-by: Roger Lu <roger.lu@mediatek.com>
* soc/mediatek/mt8192: add SPM firmwareRoger Lu2020-12-154-0/+27
| | | | | | | | | | Support SPM suspend at the end of system suspend. BUG=b:159079649,b:173653085 TEST=Asurada boots up to shell Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: I7dfa4a8a7ac585dcc8eb158d2db5a2a89436389d
* soc/mediatek/mt8192: Add 4266Mbps flag for dpm & dram blobXi Chen2020-12-157-3/+14
| | | | | | | | BUG=b:173653085 TEST=Stress pass on Asurada Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ia565eab885033a0398e2f988d56a73b90f6b1323
* soc/mediatek/mt8192: Add dpm binaryHuayang Duan2020-12-045-0/+32
| | | | | | | | | | | | | dpm release 2020-08 - Support DRAM suspend and DDR DVFS switch BUG=b:173653085 BRANCH=None TEST=Boots correctly on Asurada Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I7bb33d46a8a1447ed53af50de66e43f2b9313931
* soc/mediatek/mt8192: Add dram.elf for DRAM full calibrationHuayang Duan2020-11-265-0/+99
| | | | | | | | Add the DRAM full calibration binary 'dram.elf' to train the DDR. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I0b1db9f3dbd36d261cfcb04994d2dbb6a8838f35
* cpu/amd/model_10xx: Drop unused microcodeStefan Reinauer2020-11-118-1153/+0
| | | | | | | model_10xx was dropped from coreboot. No longer needed here. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I4ef565a6f3aa42e72ce12bf11d6e39b13b4b1697
* cpu/amd/model_fxx: Drop unused microcodeStefan Reinauer2020-11-115-443/+0
| | | | | | | model_fxx was dropped from coreboot. No longer needed here. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I439dae96cd9719ea982fbb3fca4bfe78e22566dc
* Drop geode_lxStefan Reinauer2020-11-10120-30386/+0
| | | | | | | | geode_lx has been dropped from coreboot a long time ago. Don't keep the blobs (and vsa code) around. It's all in the history. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I090a3eecada96b10933438f935539b7a25f4bfcb
* Remove execute permission from plaintext filesIdwer Vollering2020-10-17118-0/+0
| | | | | Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: Ibe3e69a546eb8bef334dac944016feefbf397d37
* Remove execute permission from all binariesAngel Pons2020-10-178-0/+0
| | | | | | | | These files aren't meant to be executed as-is. Most other binaries are not executable, so follow suit. Change-Id: I1eb433037d94af0d0b1539bea9347f503d023aa0 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
* pi/amd/00660F01/FP4/AGESA.bin: Remove execute file mode bitPaul Menzel2020-10-171-0/+0
| | | | | | | | It’s not an executable, so run `chmod -x AGESA.bin` to remove the execute file mode bit to be consistent with the other AGESA blobs. Change-Id: Ie5862c9937c1c14cca9171274df3e7bcca8dd04a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
* mainboard/amd/mandolin: add Cereme APCBFelix Held2020-09-231-0/+0
| | | | | | | | | | | | | | | The APCB (AGESA PSP Customization Block) contains no code, but only configuration information for the platform like the DRAM configuration and gets consumed by the firmware running on the PSP for the platform initialization steps that are done on the PSP. While using the Mandolin APCB on Cereme results in a booting board, it has some settings in it that are wrong for Cereme. BUG=b:159617786 TEST=Cereme boots with this APCB. Change-Id: I5d32f9614e587f8ce2bd30024c8aa8f9958e685d Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/baytrail/microcode.bin: Remove outdated microcodeArthur Heymans2020-07-263-13063/+0
| | | | | | | | | Newer microcode for family 6, model 0x37, stepping 8 can be found in the intel-microcode repo. Only stepping 3, which is presumable a pre-release model remains in 3rdparty/blobs. Change-Id: I619407f64076d7bacbaaa2f03e3875cdd05139e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
* mainboard/amd/mandolin: add Mandolin APCBNikolai Vyssotski2020-06-171-0/+0
| | | | | | | | | | | | | | | | Add Mandolin APCB binary built using the latest Mandolin AGESA APCB sources. The APCB (AGESA PSP Customization Block) contains no code, but only configuration information for the platform like the DRAM configuration and gets consumed by the firmware running on the PSP for the platform initialization steps that are done on the PSP. BUG=b:157812791 TEST=Built, booted Mandolin with this APCB Change-Id: Id7c9dbcad020f2faad9d327b014521705a45044d Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
* README.md: Make contents Markdown-friendlierAngel Pons2020-05-301-35/+36
| | | | | Change-Id: I7620e1ce43a8e7efaf96b1df0651190dd44bab62 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
* Move binary policy as READMEAngel Pons2020-05-301-2/+1
| | | | | | | | Moving this file to the top-level folder should make it more visible than hiding it inside a scary `documentation` subfolder. Change-Id: Id3c41a5a269f67f2cf7f164261203640b35e4f5f Signed-off-by: Angel Pons <th3fanbus@gmail.com>
* mb/ocp/tiogapass: Add descriptor fileDavid Hendricks2020-02-281-0/+0
| | | | | | Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: David Hendricks <dhendrix@fb.com> Change-Id: I7e4615f0516b8a9386c5c9c6aade809c27515118
* cpu/intel: Add STM SupportEugene D. Myers2019-12-173-0/+72
| | | | | | | | | | | | | | Binary STM file. Loaded by the "Add STM Support" changes into the MSEG stm.bin updated to PSTI7687 Note: this STM version has only been tested on a Minnowboard Max, Purism Librem 15v4, and a Sandybridge family CPU (Dell 990). README file added to meet the coreboot binary (blob) documentation requirements Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: Ie1a5d1a5145dbf0c0e26c93f6ffd236d5aa79f77
* mainboard/facebook/fbg1701: Add descriptor and Intel MEFrans Hendriks2019-10-313-0/+247
| | | | | | | | | | | | | | | | | | | | | These descriptor has been taken from the vendor BIOS. License.txt has been added. The person or company downloading this software (cloning the repository) is allowed to use this internally for development purposes and is bound by the restrictions imposed by this agreement. We are allowed to put the binaries on the git as long as this agreement is included as well. The blobs should not show up in a public git without this license and a coreboot image with these blobs included should always include exhibit A. That is what this agreement tries to achieve. The Intel stakeholders are aware of this and know how the blobs will be published in the 3rdparty blobs directory. BUG=N/A TEST=booting Facebook FBG1701 Change-Id: Ic03da722bc30da48ce38560745a3f89f6bd37943 Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
* Revert "mainboard/facebook/fbg1701: Add logo.bmp"Frans Hendriks2019-10-171-0/+0
| | | | | | | | | | Revert commit 283b36218bb88844dbba3379092603beb03f25f5 While waiting for Copyright, Trademark and license logo is merged. Requested info will not become available, so undo adding file. Change-Id: Ic1954761bd42e4ae089c9397ad46c677cbda4078 Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
* mainboard/facebook/fbg1701: Add logo.bmpFrans Hendriks2019-08-091-0/+0
| | | | | | | | | | Logo will be displayed during boot. BUG=N/A TEST=booting Facebook FBG1701 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: Ie8a5773e0d6cdf05934c364991168e6cd4f3b94e
* soc/mediatek/mt8183: Add SPM binariesDawei Chien2019-07-243-0/+2
| | | | | | | | | Support SPM suspend at the end of system suspend. 'pcm_allinone_lp4_3200.bin' supports LPDDR4 3200, and 'pcm_allinone_lp4_3733.bin' supports LPDDR4 3733. Change-Id: I8878a1c8460038686ad97e89ec0d7774621b8f85 Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
* soc/mediatek/mt8183: Add SSPM binaryErin Lo2019-07-173-0/+12
| | | | | | | mt8183 need sspm.bin to boot up SSPM to support MCDI Change-Id: I9b57360bb0f54beb77dd7af1778480e99e4a1ac0 Signed-off-by: Erin Lo <erin.lo@mediatek.com>
* systemagent-r6.bin: Relocate the DACHE_RAM_BASEArthur Heymans2019-06-061-0/+0
| | | | | | | | | | | | | | | | Move the DCACHE_RAM_BASE and addresses relative to that from 0xff7e0000 to 0xfeff0000. This has the advantage of having compatible CAR setup + linker symbols on both the native and mrc.bin bootpath. Another advantage is that the mrc.bin bootpath can now use more memory mapped flash. (Limit was 8M due to the location). Tested on Thinkpad T520. Change-Id: I2e1ebaedc2d99e2ad045c2dfa2e149357312fe8c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
* systemagent-r6: Move the poolArthur Heymans2019-06-061-0/+0
| | | | | | | | | | | | | | Now that the check of the pool wrt the stack is gone, the pool can be relocated from 0xff7e1000 to 0xff7f7000. The advantage is that the pool and the MRC_VAR region are now next to each other which allows coreboot to have one continuous CAR region for both coreboot (DCACHE_RAM_SIZE) and the mrc.bin (DCACHE_RAM_MRC_VAR_SIZE), which can remove the current check from the linker script. Change-Id: I8223bf6dae09b7c4accd2d23ec076600bbeb11f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
* snb/systemagent-r6: Remove stack check in GlueAllocatePoolArthur Heymans2019-06-061-0/+0
| | | | | | | | | | | | When allocating the pool, the code bails out on a signed check if (stack - pool) < 1000. The pool location is fixed at 0xff7e1000, which places restrictions on the stack location (must be above the heap). This binary patches the systemagent-r6 binary to not bail out, by changing a "JG" to "JMP". This allows to put the stack wherever we want as long as it does not collide. Change-Id: If6b4094ba0208ba14dea0bb35119906dccc4fd38 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
View Lorry Controller Status