zephyr: it8xxx2: use half space (512KB) from flash

This saved about 3 seconds erasing time while running software sync.

This also pull configurations of flash/memory layout to chip level.

BRANCH=none
BUG=b:195954913
TEST=software sync successfully.
     (without erase timeout patch of depthcharge)

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ia7fa08fdf6bdde4c47ca8d852f8eeaa83f39dae5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3097250
Reviewed-by: Denis Brockus <dbrockus@chromium.org>

4 files changed, 40 insertions, 17 deletions

diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
index 1d60630027..dab9e6b8b2 100644
--- a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
+++ b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
@@ -4,6 +4,37 @@
 
 if SOC_FAMILY_RISCV_ITE
 
+# Code RAM base for IT8XXX2
+config CROS_EC_PROGRAM_MEMORY_BASE
+	default 0x80000000
+
+# The total RAM size of IT8xxx2 is 60 KB.
+# The first 4KB block be always reserved for ram code functions,
+# so the total available RAM size will be 56KB.
+config CROS_EC_RAM_BASE
+	default 0x80101000
+
+config CROS_EC_DATA_RAM_SIZE
+	default 0x0000e000
+
+config CROS_EC_RAM_SIZE
+	default 0x0000e000
+
+# The 512KB flash space layout are as the below:
+# - RO image starts at the beginning of flash.
+# - RW image starts at the second half of flash.
+config CROS_EC_RO_MEM_OFF
+	default 0x0
+
+config CROS_EC_RO_SIZE
+	default 0x40000
+
+config CROS_EC_RW_MEM_OFF
+	default 0x40000
+
+config CROS_EC_RW_SIZE
+	default 0x40000
+
 config FLASH_LOAD_OFFSET
 	default CROS_EC_RW_MEM_OFF if CROS_EC_RW
 
diff --git a/zephyr/boards/riscv/asurada/asurada_defconfig b/zephyr/boards/riscv/asurada/asurada_defconfig
index 63fd37f073..e7f3e7f924 100644
--- a/zephyr/boards/riscv/asurada/asurada_defconfig
+++ b/zephyr/boards/riscv/asurada/asurada_defconfig
@@ -93,14 +93,3 @@ CONFIG_ITE_IT8XXX2_TIMER=y
 CONFIG_WATCHDOG=y
 CONFIG_PLATFORM_EC_WATCHDOG_PERIOD_MS=2500
 CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS=500
-
-# Code RAM base for IT8XXX2
-CONFIG_CROS_EC_PROGRAM_MEMORY_BASE=0x80000000
-CONFIG_CROS_EC_RAM_BASE=0x80100000
-CONFIG_CROS_EC_DATA_RAM_SIZE=0x00100000
-CONFIG_CROS_EC_RAM_SIZE=0x0000f000
-
-CONFIG_CROS_EC_RO_MEM_OFF=0x0
-CONFIG_CROS_EC_RO_SIZE=0x80000
-CONFIG_CROS_EC_RW_MEM_OFF=0x80000
-CONFIG_CROS_EC_RW_SIZE=0x80000
diff --git a/zephyr/include/cros/ite/it8xxx2.dtsi b/zephyr/include/cros/ite/it8xxx2.dtsi
index 7da92ea1bc..54ca7f63e3 100644
--- a/zephyr/include/cros/ite/it8xxx2.dtsi
+++ b/zephyr/include/cros/ite/it8xxx2.dtsi
@@ -69,15 +69,15 @@
 		};
 	};
 
-	/* it8xxx2 has 1MB of flash */
+	/* it8xxx2 has 1MB of flash. currently, we use 512KB from flash. */
 	binman {
 		wp-ro {
 			offset = <0x0>;
-			size = <0x80000>;
+			size = <0x40000>;
 		};
 		ec-rw {
-			offset = <0x80000>;
-			size = <0x80000>;
+			offset = <0x40000>;
+			size = <0x40000>;
 		};
 	};
 };
diff --git a/zephyr/shim/chip/it8xxx2/include/flash_chip.h b/zephyr/shim/chip/it8xxx2/include/flash_chip.h
index ff975ac439..e45a08296f 100644
--- a/zephyr/shim/chip/it8xxx2/include/flash_chip.h
+++ b/zephyr/shim/chip/it8xxx2/include/flash_chip.h
@@ -6,8 +6,11 @@
 #ifndef __CROS_EC_FLASH_CHIP_H
 #define __CROS_EC_FLASH_CHIP_H
 
-/* Flash size */
-#define CONFIG_FLASH_SIZE_BYTES         DT_REG_SIZE(DT_NODELABEL(flash0))
+/*
+ * Flash size of IT81202 is 1MB.
+ * We use only half space of flash to save time of erasing RW image from flash.
+ */
+#define CONFIG_FLASH_SIZE_BYTES         (DT_REG_SIZE(DT_NODELABEL(flash0)) / 2)
 /* Program is run directly from storage */
 #define CONFIG_MAPPED_STORAGE_BASE      DT_REG_ADDR(DT_NODELABEL(flash0))
 /*