diff options
| author | Simon Glass <sjg@chromium.org> | 2012-06-24 11:49:58 -0700 |
|---|---|---|
| committer | Gerrit <chrome-bot@google.com> | 2012-07-02 15:02:07 -0700 |
| commit | bb27b96f13541f8df5fd8c210a619705c2c24d26 (patch) | |
| tree | e516e7543e75bd485cfabdfdd8baff2ea3da04ed | |
| parent | d7dd49471c240bd8c96d67c550cc1166158b08f1 (diff) | |
| download | chrome-ec-bb27b96f13541f8df5fd8c210a619705c2c24d26.tar.gz | |
cpu: Enable reporting of faults
Faults should be enabled, otherwise we just get a hard fault whenever they
occur.
BUG=chrome-os-partner:10146
TEST=manual:
build and boot on snow; cause a fault and see that it is reported correctly
in the panic message, rather than just a hard fault.
Also tested on link, 'rw 1':
> rw 1
=== EXCEPTION: 06 ====== xPSR: 01000000 ===========
r0 :0000000b r1 :00000041 r2 :00000001 r3 :20003720
r4 :00000000 r5 :0000bbb4 r6 :2000371c r7 :00000002
r8 :00000000 r9 :20003721 r10:00000000 r11:00000000
r12:00000000 sp :200019a0 lr :00004ad1 pc :000054f6
Unaligned
mmfs = 01000000, shcsr = 00070008, hfsr = 00000000, dfsr = 00000000
Time: 0x00000000006f0938 us
Deadline: 0x00000000006ec3d4 -> -0.017764 s from now
Active timers:
Tsk 1 0x000000000072bc1e -> 0.242406
Tsk 4 0x00000000006ec3d4 -> -0.017764
Tsk 5 0x00000000007a2333 -> 0.727547
Tsk 6 0x00000000007a2193 -> 0.727131
Tsk 7 0x00000000007a1fd9 -> 0.726689
Tsk 9 0x0000000000eeb452 -> 8.366874
Task Ready Name Events Time (s)
0 R << idle >> 00000000 6.854007
1 WATCHDOG 00000000 0.000442
2 VBOOTHASH 00000000 0.286203
3 LIGHTBAR 00000000 0.018957
4 POWERSTATE 00000000 0.020656
5 TEMPSENSOR 00000000 0.000851
6 THERMAL 00000000 0.000643
7 PWM 00000000 0.000243
8 TYPEMATIC 00000000 0.000015
9 X86POWER 00000000 0.010582
10 I8042CMD 00000000 0.000015
11 HOSTCMD 00000000 0.000014
12 R CONSOLE 00000000 0.000336
13 POWERBTN 00000000 0.003883
14 KEYSCAN 00000000 0.000297
Rebooting...
Change-Id: I95a4a7fae14359aa4e2b645d2110f91161e7df88
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26170
| -rw-r--r-- | core/cortex-m/cpu.c | 4 | ||||
| -rw-r--r-- | core/cortex-m/cpu.h | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/core/cortex-m/cpu.c b/core/cortex-m/cpu.c index cae74b2cd4..edf2272256 100644 --- a/core/cortex-m/cpu.c +++ b/core/cortex-m/cpu.c @@ -12,4 +12,8 @@ void cpu_init(void) { /* Catch divide by 0 and unaligned access */ CPU_NVIC_CCR |= CPU_NVIC_CCR_DIV_0_TRAP | CPU_NVIC_CCR_UNALIGN_TRAP; + + /* Enable reporting of memory faults, bus faults and usage faults */ + CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_MEMFAULTENA | + CPU_NVIC_SHCSR_BUSFAULTENA | CPU_NVIC_SHCSR_USGFAULTENA; } diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index f84a1fdfb0..5b1046b42f 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -41,6 +41,10 @@ enum { CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31, CPU_NVIC_HFSR_FORCED = 1 << 30, CPU_NVIC_HFSR_VECTTBL = 1 << 1, + + CPU_NVIC_SHCSR_MEMFAULTENA = 1 << 16, + CPU_NVIC_SHCSR_BUSFAULTENA = 1 << 17, + CPU_NVIC_SHCSR_USGFAULTENA = 1 << 18, }; /* Set up the cpu to detect faults */ |