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| author | Louis Yung-Chieh Lo <yjlou@chromium.org> | 2012-08-17 15:46:54 +0800 |
|---|---|---|
| committer | Yung-Chieh Lo <yjlou@chromium.org> | 2012-08-26 21:24:34 -0700 |
| commit | 6dae9bd66488840021673d8e943b8f280b47a0c3 (patch) | |
| tree | 65b3e7b0ec41cdf886ea03c29c8b000e64b6e857 | |
| parent | b383d4c6b8218300c14c6f853853cc09ea761c9d (diff) | |
| download | chrome-ec-6dae9bd66488840021673d8e943b8f280b47a0c3.tar.gz | |
Snow: WP_RO should be 0x10000 (including pstate).
To reflect the CL 00799d5 that moves the pstate to 0xf000.
BUG=chrome-os-partner:12799,chrome-os-partner:11728
TEST=Build in chroot.
BRANCH=snow
snow: WP_RO is changed from 0:0xf000 --> 0:0x10000.
daisy: WP_RO is unchanged.
link: WP_RO is unchanged.
Change-Id: I572bae3f624744e60d13a762875211beffc6c516
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/30670
Reviewed-by: Vic Yang <victoryang@chromium.org>
(cherry picked from commit 9d872b724f3e4e4d49cfb9d4040f8bab609415e5)
Reviewed-on: https://gerrit.chromium.org/gerrit/31435
Reviewed-by: Cheng-Yi Chiang <cychiang@chromium.org>
| -rw-r--r-- | chip/lm4/config.h | 3 | ||||
| -rw-r--r-- | chip/stm32/config-stm32f100.h | 2 | ||||
| -rw-r--r-- | chip/stm32/config-stm32l15x.h | 2 | ||||
| -rw-r--r-- | common/flash_common.c | 4 | ||||
| -rw-r--r-- | common/fmap.c | 6 |
5 files changed, 12 insertions, 5 deletions
diff --git a/chip/lm4/config.h b/chip/lm4/config.h index ff5c5771c8..2a24fee8fb 100644 --- a/chip/lm4/config.h +++ b/chip/lm4/config.h @@ -59,6 +59,9 @@ #define CONFIG_SECTION_RW_OFF (CONFIG_SECTION_RO_OFF \ + CONFIG_SECTION_RO_SIZE) +#define CONFIG_SECTION_WP_RO_SIZE (40 * CONFIG_FLASH_BANK_SIZE) +#define CONFIG_SECTION_WP_RO_OFF CONFIG_FLASH_BASE + #ifdef CONFIG_VBOOT_SIG /* * The top of each section will hold the vboot stuff, since the firmware vector diff --git a/chip/stm32/config-stm32f100.h b/chip/stm32/config-stm32f100.h index dfb59c3cbe..21d91f6695 100644 --- a/chip/stm32/config-stm32f100.h +++ b/chip/stm32/config-stm32f100.h @@ -26,6 +26,8 @@ #define CONFIG_SECTION_RO_SIZE CONFIG_FW_RO_SIZE #define CONFIG_SECTION_RW_OFF CONFIG_FW_RW_OFF #define CONFIG_SECTION_RW_SIZE CONFIG_FW_RW_SIZE +#define CONFIG_SECTION_WP_RO_OFF CONFIG_FW_RO_OFF +#define CONFIG_SECTION_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE /* * Put this after RO to give RW more space. This also makes RO write protect diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h index 5a3fef59a8..ef913bbc0c 100644 --- a/chip/stm32/config-stm32l15x.h +++ b/chip/stm32/config-stm32l15x.h @@ -35,6 +35,8 @@ #define CONFIG_SECTION_RO_SIZE CONFIG_FW_RO_SIZE #define CONFIG_SECTION_RW_OFF CONFIG_FW_RW_OFF #define CONFIG_SECTION_RW_SIZE CONFIG_FW_RW_SIZE +#define CONFIG_SECTION_WP_RO_OFF CONFIG_FW_RO_OFF +#define CONFIG_SECTION_WP_RO_SIZE CONFIG_FW_RO_SIZE /* * The EC uses the top bank of flash to emulate a SPI-like write protect diff --git a/common/flash_common.c b/common/flash_common.c index 84a2a2d55a..d40584f279 100644 --- a/common/flash_common.c +++ b/common/flash_common.c @@ -348,8 +348,8 @@ static int flash_command_region_info(struct host_cmd_handler_args *args) r->size = CONFIG_SECTION_RW_SIZE; break; case EC_FLASH_REGION_WP_RO: - r->offset = CONFIG_SECTION_RO_OFF; - r->size = CONFIG_SECTION_RO_SIZE; + r->offset = CONFIG_SECTION_WP_RO_OFF; + r->size = CONFIG_SECTION_WP_RO_SIZE; break; default: return EC_RES_INVALID_PARAM; diff --git a/common/fmap.c b/common/fmap.c index 3adb1c1c6f..25ccc1cf70 100644 --- a/common/fmap.c +++ b/common/fmap.c @@ -105,11 +105,11 @@ const struct _ec_fmap { }, { /* The range for write protection, for factory - * finalization. Should include (or identical to) + * finalization. Should include (may be identical to) * EC_RO and aligned to hardware specification. */ .area_name = "WP_RO", - .area_offset = CONFIG_SECTION_RO_OFF, - .area_size = CONFIG_SECTION_RO_SIZE, + .area_offset = CONFIG_SECTION_WP_RO_OFF, + .area_size = CONFIG_SECTION_WP_RO_SIZE, .area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO, }, #ifdef CONFIG_VBOOT_SIG |