diff options
| author | Moritz Fischer <moritz.fischer@ettus.com> | 2019-02-20 21:38:55 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-06 06:51:33 -0800 |
| commit | 247f511b36985c840d7f70f173129e85e62fcf7f (patch) | |
| tree | 737d620b87a98ef5a1bdc7a2b3a10c1ff810e76e | |
| parent | dcd378e1cde499fe3c33efd98bd7e737b034ff77 (diff) | |
| download | chrome-ec-247f511b36985c840d7f70f173129e85e62fcf7f.tar.gz | |
chip: stm32: Fix GPIO base addresses for STM32F4/L
The CHIP_FAMILY_STM32L has the base addresses for the GPIO F, G
and H banks swapped w.r.t CHIP_FAMILY_STM32F4 and the alphabetic
order vs the base addresses.
Break out the CHIP_FAMILY_STM32F4 case in the registers file,
such that GPIOH bank works for both cases.
BUG=none
BRANCH=none
TEST=Use pin PH0 on STM32F412/11, observe it actually toggling
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Change-Id: I9a639c4872f6e4c5b384cdab9e3da2f626e32227
Reviewed-on: https://chromium-review.googlesource.com/1481650
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
| -rw-r--r-- | chip/stm32/registers.h | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index dc7a159cdb..7f86917b7e 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -260,15 +260,24 @@ #define STM32_FLASH_REGS_BASE 0x40022000 #endif -#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4) +#if defined(CHIP_FAMILY_STM32L) #define STM32_GPIOA_BASE 0x40020000 #define STM32_GPIOB_BASE 0x40020400 #define STM32_GPIOC_BASE 0x40020800 #define STM32_GPIOD_BASE 0x40020C00 #define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021400 -#define STM32_GPIOG_BASE 0x40021800 +#define STM32_GPIOF_BASE 0x40021800 /* see RM0038 table 5 */ +#define STM32_GPIOG_BASE 0x40021C00 #define STM32_GPIOH_BASE 0x40021400 +#elif defined(CHIP_FAMILY_STM32F4) +#define STM32_GPIOA_BASE 0x40020000 +#define STM32_GPIOB_BASE 0x40020400 +#define STM32_GPIOC_BASE 0x40020800 +#define STM32_GPIOD_BASE 0x40020C00 +#define STM32_GPIOE_BASE 0x40021000 +#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ +#define STM32_GPIOG_BASE 0x40021800 +#define STM32_GPIOH_BASE 0x40021C00 #elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ defined(CHIP_FAMILY_STM32L4) #define STM32_GPIOA_BASE 0x48000000 |