diff options
author | Tim Lin <tim2.lin@ite.corp-partner.google.com> | 2021-07-12 15:37:57 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-08-02 01:48:39 +0000 |
commit | 0f5662416d4bc9b0a76ac1f5b81de21bde10e28c (patch) | |
tree | 0a6564b432985882b14f1975022aa931cb43ea26 | |
parent | d842a1560cc4bb4ac4637fb4f98b827dbd0182b9 (diff) | |
download | chrome-ec-0f5662416d4bc9b0a76ac1f5b81de21bde10e28c.tar.gz |
zephyr: shi: it8xxx2: create phandle of pinmux control
Create the pinmux phandle to the SHI driver node in the
devicetree. When the pinmux_pin_set function in
cros_shi_ite_init can refer to the setting of phandle.
It is more flexible to use.
BUG=b:187541831
BRANCH=none
TEST=host command is normal.
Cq-Depend: chromium:3041210
Cq-Depend: chromium:3056118
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Change-Id: I0c71333563eb7da04d29b82767b6a6660d867eed
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3045026
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
-rw-r--r-- | zephyr/drivers/cros_shi/Kconfig | 14 | ||||
-rw-r--r-- | zephyr/drivers/cros_shi/cros_shi_it8xxx2.c | 39 | ||||
-rw-r--r-- | zephyr/dts/bindings/cros_shi/ite,it8xxx2-cros-shi.yaml | 18 | ||||
-rw-r--r-- | zephyr/include/cros/ite/it8xxx2.dtsi | 4 |
4 files changed, 69 insertions, 6 deletions
diff --git a/zephyr/drivers/cros_shi/Kconfig b/zephyr/drivers/cros_shi/Kconfig index 54c393e00f..0baa8a5d80 100644 --- a/zephyr/drivers/cros_shi/Kconfig +++ b/zephyr/drivers/cros_shi/Kconfig @@ -41,3 +41,17 @@ config CROS_SHI_IT8XXX2 help This option enables spi host interface driver which is required to communicate with the EC when the CPU is the ARM processor. + +if CROS_SHI_IT8XXX2 + +config CROS_SHI_IT8XXX2_INIT_PRIORITY + int "cros_shi it8xxx2 initialization priority" + default 52 + help + This sets the it8xxx2 cros_shi driver initialization priority. + In the GPIO shim, the alt function of SHI will be configured + as GPIO input pin. So the priority of cros_shi driver must be + lower than CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY, and + configuration these pins to alt function of SHI. + +endif # CROS_SHI_IT8XXX2 diff --git a/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c b/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c index 49184cb6fd..522d48ff09 100644 --- a/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c +++ b/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c @@ -11,6 +11,7 @@ #include <kernel.h> #include <logging/log.h> #include <soc.h> +#include <soc_dt.h> #include <drivers/pinmux.h> #include <dt-bindings/pinctrl/it8xxx2-pinctrl.h> @@ -24,6 +25,21 @@ LOG_MODULE_REGISTER(cros_shi, LOG_LEVEL_ERR); +#define DRV_CONFIG(dev) ((struct cros_shi_it8xxx2_cfg * const)(dev)->config) + +/* + * Strcture cros_shi_it8xxx2_cfg is about the setting of SHI, + * this config will be used at initial time + */ +struct cros_shi_it8xxx2_cfg { + /* Pinmux control group */ + const struct device *pinctrls; + /* GPIO pin */ + uint8_t pin; + /* Alternate function */ + uint8_t alt_fun; +}; + #define SPI_RX_MAX_FIFO_SIZE 256 #define SPI_TX_MAX_FIFO_SIZE 256 @@ -288,6 +304,7 @@ void spi_event(enum gpio_signal signal) */ static int cros_shi_ite_init(const struct device *dev) { + const struct cros_shi_it8xxx2_cfg *const config = DRV_CONFIG(dev); /* Set FIFO data target count */ struct ec_host_request cmd_head; @@ -342,12 +359,11 @@ static int cros_shi_ite_init(const struct device *dev) /* SPI slave controller enable (after settings are ready) */ IT83XX_SPI_SPISGCR = IT83XX_SPI_SPISCEN; -#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxm), okay) - const struct device *portm = DEVICE_DT_GET(DT_NODELABEL(pinmuxm)); - /* Ensure spi chip select alt function is enabled. */ - pinmux_pin_set(portm, 5, IT8XXX2_PINMUX_FUNC_1); -#endif + for (int i = 0; i < DT_INST_PROP_LEN(0, pinctrl_0); i++) { + pinmux_pin_set(config[i].pinctrls, config[i].pin, + config[i].alt_fun); + } /* Enable SPI slave interrupt */ IRQ_CONNECT(DT_INST_IRQN(0), 0, shi_ite_int_handler, 0, 0); @@ -358,7 +374,18 @@ static int cros_shi_ite_init(const struct device *dev) return 0; } -SYS_INIT(cros_shi_ite_init, POST_KERNEL, 52); + +static const struct cros_shi_it8xxx2_cfg cros_shi_cfg[] = + IT8XXX2_DT_ALT_ITEMS_LIST(0); + +#if CONFIG_CROS_SHI_IT8XXX2_INIT_PRIORITY <= \ + CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY +#error "CROS_SHI must initialize after the GPIOs initialization" +#endif +DEVICE_DT_INST_DEFINE(0, cros_shi_ite_init, NULL, + NULL, &cros_shi_cfg, POST_KERNEL, + CONFIG_CROS_SHI_IT8XXX2_INIT_PRIORITY, + NULL); /* Get protocol information */ enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args) diff --git a/zephyr/dts/bindings/cros_shi/ite,it8xxx2-cros-shi.yaml b/zephyr/dts/bindings/cros_shi/ite,it8xxx2-cros-shi.yaml new file mode 100644 index 0000000000..3e5a32f63f --- /dev/null +++ b/zephyr/dts/bindings/cros_shi/ite,it8xxx2-cros-shi.yaml @@ -0,0 +1,18 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: ITE, IT8XXX2 Serial Host Interface (SHI) node + +compatible: "ite,it8xxx2-cros-shi" + +include: base.yaml + +properties: + reg: + required: true + + pinctrl-0: + type: phandles + required: true + description: Configuration of SHI pinmux controller diff --git a/zephyr/include/cros/ite/it8xxx2.dtsi b/zephyr/include/cros/ite/it8xxx2.dtsi index 1a56d95e68..7da92ea1bc 100644 --- a/zephyr/include/cros/ite/it8xxx2.dtsi +++ b/zephyr/include/cros/ite/it8xxx2.dtsi @@ -56,6 +56,10 @@ label = "SHI"; interrupts = <171 0>; interrupt-parent = <&intc>; + pinctrl-0 = <&pinctrl_shi_mosi /* GPM0 */ + &pinctrl_shi_miso /* GPM1 */ + &pinctrl_shi_clk /* GPM4 */ + &pinctrl_shi_cs>; /* GPM5 */ }; fiu0: cros-flash@80000000 { |