diff options
| author | Tom Hughes <tomhughes@chromium.org> | 2022-10-13 16:48:46 -0700 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-10-17 16:24:54 +0000 |
| commit | e8b89860fe33529a500916ca5c9b7fba3e3deda8 (patch) | |
| tree | 57790285e51061ffef696099622e07b8ae2ec735 | |
| parent | c606b02622d6aea49b2081864121ccc9173b6da9 (diff) | |
| download | chrome-ec-e8b89860fe33529a500916ca5c9b7fba3e3deda8.tar.gz | |
tree: Remove chip/mec1322 and references
There are no longer any boards that use chip/mec1322.
BRANCH=none
BUG=none
TEST=CQ passes
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ie03535c6c62c61c86fc2714ec4e7bc48eb0e2d79
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3953934
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
31 files changed, 1 insertions, 5322 deletions
diff --git a/chip/mec1322/adc.c b/chip/mec1322/adc.c deleted file mode 100644 index 8f5df03ee1..0000000000 --- a/chip/mec1322/adc.c +++ /dev/null @@ -1,81 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "common.h" -#include "console.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* - * Conversion on a single channel takes less than 12 ms. Set timeout to - * 15 ms so that we have a 3-ms margin. - */ -#define ADC_SINGLE_READ_TIME 15000 - -struct mutex adc_lock; - -static volatile task_id_t task_waiting; - -static int start_single_and_wait(int timeout) -{ - int event; - - task_waiting = task_get_current(); - - /* Start conversion */ - MEC1322_ADC_CTRL |= BIT(1); - - /* Wait for interrupt */ - event = task_wait_event(timeout); - task_waiting = TASK_ID_INVALID; - return event != TASK_EVENT_TIMER; -} - -int adc_read_channel(enum adc_channel ch) -{ - const struct adc_t *adc = adc_channels + ch; - int value; - - mutex_lock(&adc_lock); - - MEC1322_ADC_SINGLE = 1 << adc->channel; - - if (start_single_and_wait(ADC_SINGLE_READ_TIME)) - value = MEC1322_ADC_READ(adc->channel) * adc->factor_mul / - adc->factor_div + - adc->shift; - else - value = ADC_READ_ERROR; - - mutex_unlock(&adc_lock); - return value; -} - -static void adc_init(void) -{ - /* Activate ADC module */ - MEC1322_ADC_CTRL |= BIT(0); - - /* Enable interrupt */ - task_waiting = TASK_ID_INVALID; - MEC1322_INT_ENABLE(17) |= BIT(10); - MEC1322_INT_BLK_EN |= BIT(17); - task_enable_irq(MEC1322_IRQ_ADC_SNGL); -} -DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); - -static void adc_interrupt(void) -{ - /* Clear interrupt status bit */ - MEC1322_ADC_CTRL |= BIT(7); - - if (task_waiting != TASK_ID_INVALID) - task_wake(task_waiting); -} -DECLARE_IRQ(MEC1322_IRQ_ADC_SNGL, adc_interrupt, 2); diff --git a/chip/mec1322/adc_chip.h b/chip/mec1322/adc_chip.h deleted file mode 100644 index d8ade540a8..0000000000 --- a/chip/mec1322/adc_chip.h +++ /dev/null @@ -1,27 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MEC1322-specific ADC module for Chrome EC */ - -#ifndef __CROS_EC_ADC_CHIP_H -#define __CROS_EC_ADC_CHIP_H - -/* Data structure to define ADC channels. */ -struct adc_t { - const char *name; - int factor_mul; - int factor_div; - int shift; - int channel; -}; - -/* Minimum and maximum values returned by adc_read_channel(). */ -#define ADC_READ_MIN 0 -#define ADC_READ_MAX 1023 - -/* Just plain id mapping for code readability */ -#define MEC1322_ADC_CH(x) (x) - -#endif /* __CROS_EC_ADC_CHIP_H */ diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk deleted file mode 100644 index 7fa324fea1..0000000000 --- a/chip/mec1322/build.mk +++ /dev/null @@ -1,79 +0,0 @@ -# -*- makefile -*- -# Copyright 2013 The ChromiumOS Authors -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# MEC1322 chip specific files build -# - -# MEC1322 SoC has a Cortex-M4 ARM core -CORE:=cortex-m -# Allow the full Cortex-M4 instruction set -CFLAGS_CPU+=-mcpu=cortex-m4 - -ifeq ($(CONFIG_LTO),y) -# Re-include the core's build.mk file so we can remove the lto flag. -include core/$(CORE)/build.mk -endif - -# Required chip modules -chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o -chip-$(CONFIG_ADC)+=adc.o -chip-$(CONFIG_FANS)+=fan.o -chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o -chip-$(CONFIG_I2C)+=i2c.o -chip-$(CONFIG_HOST_INTERFACE_LPC)+=lpc.o -chip-$(CONFIG_PWM)+=pwm.o -chip-$(CONFIG_WATCHDOG)+=watchdog.o -ifndef CONFIG_KEYBOARD_DISCRETE -chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o -endif -chip-$(CONFIG_DMA)+=dma.o -chip-$(CONFIG_SPI)+=spi.o - -# location of the scripts and keys used to pack the SPI flash image -SCRIPTDIR:=./chip/${CHIP}/util - -# Allow SPI size to be overridden by board specific size, default to 256KB. -CHIP_SPI_SIZE_KB?=256 - -# Commands to convert $^ to $@.tmp -cmd_obj_to_bin = $(OBJCOPY) --gap-fill=0xff -O binary $< $@.tmp1 ; \ - ${SCRIPTDIR}/pack_ec.py -o $@.tmp -i $@.tmp1 \ - --loader_file $(mec1322-lfw-flat) \ - --payload_key ${SCRIPTDIR}/rsakey_sign_payload.pem \ - --header_key ${SCRIPTDIR}/rsakey_sign_header.pem \ - --spi_size ${CHIP_SPI_SIZE_KB} \ - --image_size $(_rw_size); rm -f $@.tmp1 - -mec1322-lfw = chip/mec1322/lfw/ec_lfw -mec1322-lfw-flat = $(out)/RW/$(mec1322-lfw)-lfw.flat - -# build these specifically for lfw with -lfw suffix -objs_lfw = $(patsubst %, $(out)/RW/%-lfw.o, \ - $(addprefix common/, util gpio) \ - $(addprefix chip/$(CHIP)/, spi dma gpio clock hwtimer) \ - core/$(CORE)/cpu $(mec1322-lfw)) - -# reuse version.o (and its dependencies) from main board -objs_lfw += $(out)/RW/common/version.o - -dirs-y+=chip/$(CHIP)/lfw - -# objs with -lfw suffix are to include lfw's gpio -$(out)/RW/%-lfw.o: private CC+=-I$(BDIR)/lfw -DLFW=$(EMPTY) -# Remove the lto flag for the loader. It actually causes it to bloat in size. -ifeq ($(CONFIG_LTO),y) -$(out)/RW/%-lfw.o: private CFLAGS_CPU := $(filter-out -flto, $(CFLAGS_CPU)) -endif -$(out)/RW/%-lfw.o: %.c - $(call quiet,c_to_o,CC ) - -# let lfw's elf link only with selected objects -$(out)/RW/%-lfw.elf: private objs = $(objs_lfw) -$(out)/RW/%-lfw.elf: override shlib := -$(out)/RW/%-lfw.elf: %.ld $(objs_lfw) - $(call quiet,elf,LD ) - -# final image needs lfw loader -$(out)/$(PROJECT).bin: $(mec1322-lfw-flat) diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c deleted file mode 100644 index c9fc68d58a..0000000000 --- a/chip/mec1322/clock.c +++ /dev/null @@ -1,473 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "builtin/assert.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "shared_mem.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "uart.h" -#include "util.h" -#include "vboot_hash.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) - -#ifdef CONFIG_LOW_POWER_IDLE -/* Recovery time for HvySlp2 is 0 usec */ -#define HEAVY_SLEEP_RECOVER_TIME_USEC 75 - -#define SET_HTIMER_DELAY_USEC 200 - -static int idle_sleep_cnt; -static int idle_dsleep_cnt; -static uint64_t total_idle_dsleep_time_us; - -/* - * Fixed amount of time to keep the console in use flag true after boot in - * order to give a permanent window in which the heavy sleep mode is not used. - */ -#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND) -static int console_in_use_timeout_sec = 60; -static timestamp_t console_expire_time; -#endif /*CONFIG_LOW_POWER_IDLE */ - -static int freq = 48000000; - -void clock_wait_cycles(uint32_t cycles) -{ - asm volatile("1: subs %0, #1\n" - " bne 1b\n" - : "+r"(cycles)); -} - -int clock_get_freq(void) -{ - return freq; -} - -void clock_init(void) -{ -#ifdef CONFIG_CLOCK_CRYSTAL - /* XOSEL: 0 = Parallel resonant crystal */ - MEC1322_VBAT_CE &= ~0x1; -#else - /* XOSEL: 1 = Single ended clock source */ - MEC1322_VBAT_CE |= 0x1; -#endif - - /* 32K clock enable */ - MEC1322_VBAT_CE |= 0x2; - -#ifdef CONFIG_CLOCK_CRYSTAL - /* Wait for crystal to stabilize (OSC_LOCK == 1) */ - while (!(MEC1322_PCR_CHIP_OSC_ID & 0x100)) - ; -#endif -} - -/** - * Speed through boot + vboot hash calculation, dropping our processor clock - * only after vboot hashing is completed. - */ -static void clock_turbo_disable(void); -DECLARE_DEFERRED(clock_turbo_disable); - -static void clock_turbo_disable(void) -{ -#ifdef CONFIG_VBOOT_HASH - if (vboot_hash_in_progress()) - hook_call_deferred(&clock_turbo_disable_data, 100 * MSEC); - else -#endif - /* Use 12 MHz processor clock for power savings */ - MEC1322_PCR_PROC_CLK_CTL = 4; -} -DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1); - -#ifdef CONFIG_LOW_POWER_IDLE -/** - * initialization of Hibernation timer - */ -static void htimer_init(void) -{ - MEC1322_INT_BLK_EN |= BIT(17); - MEC1322_INT_ENABLE(17) |= BIT(20); /* GIRQ=17, aggregator bit = 20 */ - MEC1322_HTIMER_PRELOAD = 0; /* disable at beginning */ - - task_enable_irq(MEC1322_IRQ_HTIMER); -} - -/** - * Use hibernate module to set up an htimer interrupt at a given - * time from now - * - * @param seconds Number of seconds before htimer interrupt - * @param microseconds Number of microseconds before htimer interrupt - */ -static void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds) -{ - if (seconds || microseconds) { - if (seconds > 2) { - /* count from 2 sec to 2 hrs, mec1322 sec 18.10.2 */ - ASSERT(seconds <= 0xffff / 8); - MEC1322_HTIMER_CONTROL = 1; /* 0.125(=1/8) per clock */ - /* (number of counts to be loaded) - * = seconds * ( 8 clocks per second ) - * + microseconds / 125000 - * ---> (0 if (microseconds < 125000) - */ - MEC1322_HTIMER_PRELOAD = - (seconds * 8 + microseconds / 125000); - - } else { /* count up to 2 sec. */ - - MEC1322_HTIMER_CONTROL = 0; /* 30.5(= 2/61) usec */ - - /* (number of counts to be loaded) - * = (total microseconds) / 30.5; - */ - MEC1322_HTIMER_PRELOAD = - (seconds * 1000000 + microseconds) * 2 / 61; - } - } -} - -/** - * return time slept in micro-seconds - */ -static timestamp_t system_get_htimer(void) -{ - uint16_t count; - timestamp_t time; - - count = MEC1322_HTIMER_COUNT; - - if (MEC1322_HTIMER_CONTROL == 1) /* if > 2 sec */ - /* 0.125 sec per count */ - time.le.lo = (uint32_t)(count * 125000); - else /* if < 2 sec */ - /* 30.5(=61/2)usec per count */ - time.le.lo = (uint32_t)(count * 61 / 2); - - time.le.hi = 0; - - return time; /* in uSec */ -} - -/** - * Disable and clear hibernation timer interrupt - */ -static void system_reset_htimer_alarm(void) -{ - MEC1322_HTIMER_PRELOAD = 0; -} - -/** - * This is mec1322 specific and equivalent to ARM Cortex's - * 'DeepSleep' via system control block register, CPU_SCB_SYSCTRL - */ -static void prepare_for_deep_sleep(void) -{ - uint32_t ec_slp_en = MEC1322_PCR_EC_SLP_EN | - MEC1322_PCR_EC_SLP_EN_SLEEP; - - /* sysTick timer */ - CPU_NVIC_ST_CTRL &= ~ST_ENABLE; - CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG; - - /* Disable JTAG */ - MEC1322_EC_JTAG_EN &= ~1; - /* Power down ADC VREF, ADC_VREF overrides ADC_CTRL. */ - MEC1322_EC_ADC_VREF_PD |= 1; - - /* Stop watchdog */ - MEC1322_WDG_CTL &= ~1; - - /* Stop timers */ - MEC1322_TMR32_CTL(0) &= ~1; - MEC1322_TMR32_CTL(1) &= ~1; - MEC1322_TMR16_CTL(0) &= ~1; - - MEC1322_PCR_CHIP_SLP_EN |= 0x3; -#ifdef CONFIG_PWM - if (pwm_get_keep_awake_mask()) - ec_slp_en &= ~pwm_get_keep_awake_mask(); - else -#endif - /* Disable 100 Khz clock */ - MEC1322_PCR_SLOW_CLK_CTL &= 0xFFFFFC00; - - MEC1322_PCR_EC_SLP_EN = ec_slp_en; - MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP; - MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP; - -#ifndef CONFIG_POWER_S0IX - MEC1322_LPC_ACT = 0x0; -#endif - - MEC1322_PCR_SYS_SLP_CTL = 0x2; /* heavysleep 2 */ - - CPU_NVIC_ST_CTRL &= ~ST_TICKINT; /* SYS_TICK_INT_DISABLE */ -} - -static void resume_from_deep_sleep(void) -{ - CPU_NVIC_ST_CTRL |= ST_TICKINT; /* SYS_TICK_INT_ENABLE */ - CPU_NVIC_ST_CTRL |= ST_ENABLE; - - MEC1322_EC_JTAG_EN = 1; - MEC1322_EC_ADC_VREF_PD &= ~1; - /* ADC_VREF_PD overrides ADC_CTRL ! */ - - /* Enable timer */ - MEC1322_TMR32_CTL(0) |= 1; - MEC1322_TMR32_CTL(1) |= 1; - MEC1322_TMR16_CTL(0) |= 1; - - /* Enable watchdog */ - MEC1322_WDG_CTL |= 1; - - MEC1322_PCR_SLOW_CLK_CTL |= 0x1e0; - MEC1322_PCR_CHIP_SLP_EN &= ~0x3; - MEC1322_PCR_EC_SLP_EN &= MEC1322_PCR_EC_SLP_EN_WAKE; - MEC1322_PCR_HOST_SLP_EN &= MEC1322_PCR_HOST_SLP_EN_WAKE; - MEC1322_PCR_EC_SLP_EN2 &= MEC1322_PCR_EC_SLP_EN2_WAKE; - - MEC1322_PCR_SYS_SLP_CTL = 0xF8; /* default */ - -#ifndef CONFIG_POWER_S0IX - /* Enable LPC */ - MEC1322_LPC_ACT |= 1; -#endif -} - -void clock_refresh_console_in_use(void) -{ - disable_sleep(SLEEP_MASK_CONSOLE); - - /* Set console in use expire time. */ - console_expire_time = get_time(); - console_expire_time.val += console_in_use_timeout_sec * SECOND; -} - -/** - * Low power idle task. Executed when no tasks are ready to be scheduled. - */ -void __idle(void) -{ - timestamp_t t0; - timestamp_t t1; - timestamp_t ht_t1; - uint32_t next_delay; - uint32_t max_sleep_time; - int time_for_dsleep; - int uart_ready_for_deepsleep; - - htimer_init(); /* hibernation timer initialize */ - - disable_sleep(SLEEP_MASK_CONSOLE); - console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME; - - /* - * Print when the idle task starts. This is the lowest priority task, - * so this only starts once all other tasks have gotten a chance to do - * their task inits and have gone to sleep. - */ - CPRINTS("low power idle task started"); - - while (1) { - /* Disable interrupts */ - interrupt_disable(); - - t0 = get_time(); /* uSec */ - - /* __hw_clock_event_get() is next programmed timer event */ - next_delay = __hw_clock_event_get() - t0.le.lo; - - time_for_dsleep = next_delay > (HEAVY_SLEEP_RECOVER_TIME_USEC + - SET_HTIMER_DELAY_USEC); - - max_sleep_time = next_delay - HEAVY_SLEEP_RECOVER_TIME_USEC; - - /* check if there enough time for deep sleep */ - if (DEEP_SLEEP_ALLOWED && time_for_dsleep) { - /* - * Check if the console use has expired and console - * sleep is masked by GPIO(UART-RX) interrupt. - */ - if ((sleep_mask & SLEEP_MASK_CONSOLE) && - t0.val > console_expire_time.val) { - /* allow console to sleep. */ - enable_sleep(SLEEP_MASK_CONSOLE); - - /* - * Wait one clock before checking if heavy sleep - * is allowed to give time for sleep mask - * to be updated. - */ - clock_wait_cycles(1); - - if (LOW_SPEED_DEEP_SLEEP_ALLOWED) - CPRINTS("Disable console in deepsleep"); - } - - /* UART is not being used */ - uart_ready_for_deepsleep = - LOW_SPEED_DEEP_SLEEP_ALLOWED && - !uart_tx_in_progress() && uart_buffer_empty(); - - /* - * Since MEC1322's heavysleep modes requires all block - * to be sleepable, UART/console's readiness is final - * decision factor of heavysleep of EC. - */ - if (uart_ready_for_deepsleep) { - idle_dsleep_cnt++; - - /* - * config UART Rx as GPIO wakeup interrupt - * source - */ - uart_enter_dsleep(); - - /* MEC1322 specific deep-sleep mode */ - prepare_for_deep_sleep(); - - /* - * 'max_sleep_time' value should be big - * enough so that hibernation timer's interrupt - * triggers only after 'wfi' completes its - * excution. - */ - max_sleep_time -= (get_time().le.lo - t0.le.lo); - - /* setup/enable htimer wakeup interrupt */ - system_set_htimer_alarm(0, max_sleep_time); - } else { - idle_sleep_cnt++; - } - - /* Wait for interrupt: goes into deep sleep. */ - cpu_enter_suspend_mode(); - - if (uart_ready_for_deepsleep) { - resume_from_deep_sleep(); - - /* - * Fast forward timer according to htimer - * counter: - * Since all blocks including timers will be in - * sleep mode, timers stops except hibernate - * timer. - * And system schedule timer should be corrected - * after wakeup by either hibernate timer or - * GPIO_UART_RX interrupt. - */ - ht_t1 = system_get_htimer(); - - /* disable/clear htimer wakeup interrupt */ - system_reset_htimer_alarm(); - - t1.val = t0.val + (uint64_t)(max_sleep_time - - ht_t1.le.lo); - - force_time(t1); - - /* re-eanble UART */ - uart_exit_dsleep(); - - /* Record time spent in deep sleep. */ - total_idle_dsleep_time_us += - (uint64_t)(max_sleep_time - - ht_t1.le.lo); - } - - } else { /* CPU 'Sleep' mode */ - idle_sleep_cnt++; - cpu_enter_suspend_mode(); - } - - interrupt_enable(); - } /* while(1) */ -} - -#ifdef CONFIG_CMD_IDLE_STATS -/** - * Print low power idle statistics - */ -static int command_idle_stats(int argc, const char **argv) -{ - timestamp_t ts = get_time(); - - ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); - ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); - - ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n", - total_idle_dsleep_time_us); - ccprintf("Total time on: %.6llds\n\n", ts.val); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", - "Print last idle stats"); -#endif /* defined(CONFIG_CMD_IDLE_STATS) */ - -/** - * Configure deep sleep clock settings. - */ -static int command_dsleep(int argc, const char **argv) -{ - int v; - - if (argc > 1) { - if (parse_bool(argv[1], &v)) { - /* - * Force deep sleep not to use heavy sleep mode or - * allow it to use the heavy sleep mode. - */ - if (v) /* 'on' */ - disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED); - else /* 'off' */ - enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED); - } else { - /* Set console in use timeout. */ - char *e; - v = strtoi(argv[1], &e, 10); - if (*e) - return EC_ERROR_PARAM1; - - console_in_use_timeout_sec = v; - - /* Refresh console in use to use new timeout. */ - clock_refresh_console_in_use(); - } - } - - ccprintf("Sleep mask: %08x\n", sleep_mask); - ccprintf("Console in use timeout: %d sec\n", - console_in_use_timeout_sec); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, "[ on | off | <timeout> sec]", - "Deep sleep clock settings:\nUse 'on' to force deep " - "sleep NOT to enter heavysleep mode.\nUse 'off' to " - "allow deep sleep to use heavysleep whenever conditions" - "allow.\n" - "Give a timeout value for the console in use timeout.\n" - "See also 'sleepmask'."); -#endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h deleted file mode 100644 index 027109cded..0000000000 --- a/chip/mec1322/config_chip.h +++ /dev/null @@ -1,112 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_H -#define __CROS_EC_CONFIG_CHIP_H - -/* CPU core BFD configuration */ -#include "core/cortex-m/config_core.h" - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 93 - -/* Use a bigger console output buffer */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 - -/* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 250 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) - -/* - * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one - * additional port. - */ -#define CONFIG_I2C_MULTI_PORT_CONTROLLER - -#define I2C_CONTROLLER_COUNT 4 -#define I2C_PORT_COUNT 5 - -/****************************************************************************/ -/* Memory mapping */ - -/* - * The memory region for RAM is actually 0x00100000-0x00120000. - * RAM for RO/RW = 20k - * CODE size of the Loader is 3k - * As per the above configuartion the upper 20k - * is used to store data.The rest is for code. - * the lower 107K is flash[ 3k Loader and 104k RO/RW], - * and the higher 20K is RAM shared by loader and RO/RW. - */ - -/****************************************************************************/ -/* Define our RAM layout. */ - -#define CONFIG_MEC_SRAM_BASE_START 0x00100000 -#define CONFIG_MEC_SRAM_BASE_END 0x00120000 -#define CONFIG_MEC_SRAM_SIZE \ - (CONFIG_MEC_SRAM_BASE_END - CONFIG_MEC_SRAM_BASE_START) - -/* 20k RAM for RO / RW / loader */ -#define CONFIG_RAM_SIZE 0x00005000 -#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - CONFIG_RAM_SIZE) - -/* System stack size */ -#define CONFIG_STACK_SIZE 1024 - -/* non-standard task stack sizes */ -#define IDLE_TASK_STACK_SIZE 512 -#define LARGER_TASK_STACK_SIZE 640 - -#define CHARGER_TASK_STACK_SIZE 640 -#define HOOKS_TASK_STACK_SIZE 640 -#define CONSOLE_TASK_STACK_SIZE 640 -#define HOST_CMD_TASK_STACK_SIZE 640 - -/* - * TODO: Large stack consumption - * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245 - */ -#define PD_TASK_STACK_SIZE 800 - -/* Default task stack size */ -#define TASK_STACK_SIZE 512 - -/****************************************************************************/ -/* Define our flash layout. */ - -/* Protect bank size 4K bytes */ -#define CONFIG_FLASH_BANK_SIZE 0x00001000 -/* Sector erase size 4K bytes */ -#define CONFIG_FLASH_ERASE_SIZE 0x00001000 -/* Minimum write size */ -#define CONFIG_FLASH_WRITE_SIZE 0x00000004 - -/* One page size for write */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 - -/* Program memory base address */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000 - -#include "config_flash_layout.h" - -/****************************************************************************/ -/* Customize the build */ -/* Optional features present on this chip */ -#if 0 -#define CONFIG_ADC -#define CONFIG_PECI -#define CONFIG_MPU -#endif -#define CONFIG_DMA -#define CONFIG_HOST_INTERFACE_LPC -#define CONFIG_SPI -#define CONFIG_SWITCH - -#define GPIO_PIN(index) (index / 10), (1 << (index % 10)) -#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) - -#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h deleted file mode 100644 index 3ab03325aa..0000000000 --- a/chip/mec1322/config_flash_layout.h +++ /dev/null @@ -1,64 +0,0 @@ -/* Copyright 2015 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H -#define __CROS_EC_CONFIG_FLASH_LAYOUT_H - -/* - * mec1322 flash layout: - * - Non memory-mapped, external SPI. - * - RW image at the beginning of writable region. - * - Bootloader at the beginning of protected region, followed by RO image. - * - Loader + (RO | RW) loaded into program memory. - */ - -/* Non-memmapped, external SPI */ -#define CONFIG_EXTERNAL_STORAGE -#undef CONFIG_MAPPED_STORAGE -#undef CONFIG_FLASH_PSTATE -#define CONFIG_SPI_FLASH - -/* EC region of SPI resides at end of ROM, protected region follows writable */ -#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000) -#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000) -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 - -/* Loader resides at the beginning of program memory */ -#define CONFIG_LOADER_MEM_OFF 0 -#define CONFIG_LOADER_SIZE 0xC00 - -/* Write protect Loader and RO Image */ -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -/* - * Write protect 128k section of 256k physical flash which contains loader - * and RO Images. - */ -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -/* - * RO / RW images follow the loader in program memory. Either RO or RW - * image will be loaded -- both cannot be loaded at the same time. - */ -#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + CONFIG_LOADER_SIZE) -#define CONFIG_RO_SIZE (97 * 1024) -#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF -#define CONFIG_RW_SIZE CONFIG_RO_SIZE - -/* WP region consists of second half of SPI, and begins with the boot header */ -#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 -#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240 - -/* Loader / lfw image immediately follows the boot header on SPI */ -#define CONFIG_LOADER_STORAGE_OFF \ - (CONFIG_BOOT_HEADER_STORAGE_OFF + CONFIG_BOOT_HEADER_STORAGE_SIZE) - -/* RO image immediately follows the loader image */ -#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + CONFIG_LOADER_SIZE) - -/* RW image starts at the beginning of SPI */ -#define CONFIG_RW_STORAGE_OFF 0 - -#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */ diff --git a/chip/mec1322/dma.c b/chip/mec1322/dma.c deleted file mode 100644 index 20ab3cf9ef..0000000000 --- a/chip/mec1322/dma.c +++ /dev/null @@ -1,159 +0,0 @@ -/* Copyright 2014 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTS(format, args...) cprints(CC_DMA, format, ##args) - -mec1322_dma_chan_t *dma_get_channel(enum dma_channel channel) -{ - mec1322_dma_regs_t *dma = MEC1322_DMA_REGS; - - return &dma->chan[channel]; -} - -void dma_disable(enum dma_channel channel) -{ - mec1322_dma_chan_t *chan = dma_get_channel(channel); - - if (chan->ctrl & BIT(0)) - chan->ctrl &= ~BIT(0); - - if (chan->act == 1) - chan->act = 0; -} - -void dma_disable_all(void) -{ - int ch; - mec1322_dma_regs_t *dma; - - for (ch = 0; ch < MEC1322_DMAC_COUNT; ch++) { - mec1322_dma_chan_t *chan = dma_get_channel(ch); - /* Abort any current transfer. */ - chan->ctrl |= BIT(25); - /* Disable the channel. */ - chan->ctrl &= ~BIT(0); - chan->act = 0; - } - - /* Soft-reset the block. */ - dma = MEC1322_DMA_REGS; - dma->ctrl |= 0x2; -} - -/** - * Prepare a channel for use and start it - * - * @param chan Channel to read - * @param count Number of bytes to transfer - * @param periph Pointer to peripheral data register - * @param memory Pointer to memory address for receive/transmit - * @param flags DMA flags for the control register, normally: - * MEC1322_DMA_INC_MEM | MEC1322_DMA_TO_DEV for tx - * MEC1322_DMA_INC_MEM for rx - */ -static void prepare_channel(mec1322_dma_chan_t *chan, unsigned count, - void *periph, void *memory, unsigned flags) -{ - int xfer_size = (flags >> 20) & 0x7; - - if (chan->ctrl & BIT(0)) - chan->ctrl &= ~BIT(0); - - chan->act |= 0x1; - chan->dev = (uint32_t)periph; - chan->mem_start = MEC1322_RAM_ALIAS((uint32_t)memory); - chan->mem_end = MEC1322_RAM_ALIAS((uint32_t)memory) + xfer_size * count; - chan->ctrl = flags; -} - -void dma_go(mec1322_dma_chan_t *chan) -{ - /* Flush data in write buffer so that DMA can get the latest data */ - asm volatile("dsb;"); - - /* Fire it up */ - chan->ctrl |= MEC1322_DMA_RUN; -} - -void dma_prepare_tx(const struct dma_option *option, unsigned count, - const void *memory) -{ - mec1322_dma_chan_t *chan = dma_get_channel(option->channel); - - /* - * Cast away const for memory pointer; this is ok because we know - * we're preparing the channel for transmit. - */ - prepare_channel(chan, count, option->periph, (void *)memory, - MEC1322_DMA_INC_MEM | MEC1322_DMA_TO_DEV | - MEC1322_DMA_DEV(option->channel) | - option->flags); -} - -void dma_start_rx(const struct dma_option *option, unsigned count, void *memory) -{ - mec1322_dma_chan_t *chan; - - chan = dma_get_channel(option->channel); - - prepare_channel(chan, count, option->periph, memory, - MEC1322_DMA_INC_MEM | MEC1322_DMA_DEV(option->channel) | - option->flags); - dma_go(chan); -} - -int dma_bytes_done(mec1322_dma_chan_t *chan, int orig_count) -{ - int xfer_size = (chan->ctrl >> 20) & 0x7; - - return orig_count - (chan->mem_end - chan->mem_start) / xfer_size; -} - -bool dma_is_enabled(mec1322_dma_chan_t *chan) -{ - return (chan->ctrl & MEC1322_DMA_RUN); -} - -void dma_init(void) -{ - mec1322_dma_regs_t *dma = MEC1322_DMA_REGS; - dma->ctrl |= 0x1; -} - -int dma_wait(enum dma_channel channel) -{ - mec1322_dma_chan_t *chan = dma_get_channel(channel); - timestamp_t deadline; - - if (chan->act == 0) - return EC_SUCCESS; - - deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US; - while (!(chan->int_status & 0x4)) { - if (deadline.val <= get_time().val) - return EC_ERROR_TIMEOUT; - - udelay(DMA_POLLING_INTERVAL_US); - } - return EC_SUCCESS; -} - -void dma_clear_isr(enum dma_channel channel) -{ - mec1322_dma_chan_t *chan = dma_get_channel(channel); - - chan->int_status |= 0x4; -} diff --git a/chip/mec1322/fan.c b/chip/mec1322/fan.c deleted file mode 100644 index 543a9b8ca6..0000000000 --- a/chip/mec1322/fan.c +++ /dev/null @@ -1,158 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MEC1322 fan control module. */ - -/* This assumes 2-pole fan. For each rotation, 5 edges are measured. */ - -#include "fan.h" -#include "registers.h" -#include "util.h" - -/* Maximum tach reading/target value */ -#define MAX_TACH 0x1fff - -/* Tach target value for disable fan */ -#define FAN_OFF_TACH 0xfff8 - -/* - * RPM = (n - 1) * m * f * 60 / poles / TACH - * n = number of edges = 5 - * m = multiplier defined by RANGE = 2 in our case - * f = 32.768K - * poles = 2 - */ -#define RPM_TO_TACH(rpm) MIN((7864320 / MAX((rpm), 1)), MAX_TACH) -#define TACH_TO_RPM(tach) (7864320 / MAX((tach), 1)) - -static int rpm_setting; -static int duty_setting; -static int in_rpm_mode = 1; - -static void clear_status(void) -{ - /* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */ - MEC1322_FAN_STATUS = 0x23; -} - -void fan_set_enabled(int ch, int enabled) -{ - if (in_rpm_mode) { - if (enabled) - fan_set_rpm_target(ch, rpm_setting); - else - MEC1322_FAN_TARGET = FAN_OFF_TACH; - } else { - if (enabled) - fan_set_duty(ch, duty_setting); - else - MEC1322_FAN_SETTING = 0; - } - clear_status(); -} - -int fan_get_enabled(int ch) -{ - if (in_rpm_mode) - return (MEC1322_FAN_TARGET & 0xff00) != 0xff00; - else - return !!MEC1322_FAN_SETTING; -} - -void fan_set_duty(int ch, int percent) -{ - if (percent < 0) - percent = 0; - else if (percent > 100) - percent = 100; - - duty_setting = percent; - MEC1322_FAN_SETTING = percent * 255 / 100; - clear_status(); -} - -int fan_get_duty(int ch) -{ - return duty_setting; -} - -int fan_get_rpm_mode(int ch) -{ - return !!(MEC1322_FAN_CFG1 & BIT(7)); -} - -void fan_set_rpm_mode(int ch, int rpm_mode) -{ - if (rpm_mode) - MEC1322_FAN_CFG1 |= BIT(7); - else - MEC1322_FAN_CFG1 &= ~BIT(7); - clear_status(); -} - -int fan_get_rpm_actual(int ch) -{ - if ((MEC1322_FAN_READING >> 8) == 0xff) - return 0; - else - return TACH_TO_RPM(MEC1322_FAN_READING >> 3); -} - -int fan_get_rpm_target(int ch) -{ - return rpm_setting; -} - -void fan_set_rpm_target(int ch, int rpm) -{ - rpm_setting = rpm; - MEC1322_FAN_TARGET = RPM_TO_TACH(rpm) << 3; - clear_status(); -} - -enum fan_status fan_get_status(int ch) -{ - uint8_t sts = MEC1322_FAN_STATUS; - - if (sts & (BIT(5) | BIT(1))) - return FAN_STATUS_FRUSTRATED; - if (fan_get_rpm_actual(ch) == 0) - return FAN_STATUS_STOPPED; - return FAN_STATUS_LOCKED; -} - -int fan_is_stalled(int ch) -{ - uint8_t sts = MEC1322_FAN_STATUS; - if (fan_get_rpm_actual(ch)) { - MEC1322_FAN_STATUS = 0x1; - return 0; - } - return sts & 0x1; -} - -void fan_channel_setup(int ch, unsigned int flags) -{ - /* - * Fan configuration 1 register: - * 0x80 = bit 7 = RPM mode (0x00 if FAN_USE_RPM_MODE not set) - * 0x20 = bits 6:5 = min 1000 RPM, multiplier = 2 - * 0x08 = bits 4:3 = 5 edges, 2 poles - * 0x03 = bits 2:0 = 400 ms update time - * - * Fan configuration 2 register: - * 0x00 = bit 6 = Ramp control disabled - * 0x00 = bit 5 = Glitch filter enabled - * 0x18 = bits 4:3 = Using both derivative options - * 0x02 = bits 2:1 = error range is 50 RPM - * 0x00 = bits 0 = normal polarity - */ - if (flags & FAN_USE_RPM_MODE) - MEC1322_FAN_CFG1 = 0xab; - else - MEC1322_FAN_CFG1 = 0x2b; - MEC1322_FAN_CFG2 = 0x1a; - clear_status(); -} diff --git a/chip/mec1322/flash.c b/chip/mec1322/flash.c deleted file mode 100644 index 4b5b622389..0000000000 --- a/chip/mec1322/flash.c +++ /dev/null @@ -1,267 +0,0 @@ -/* Copyright 2015 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "flash.h" -#include "host_command.h" -#include "shared_mem.h" -#include "spi.h" -#include "spi_flash.h" -#include "system.h" -#include "util.h" -#include "hooks.h" - -#define PAGE_SIZE 256 - -#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */ -#define FLASH_HOOK_VERSION 1 - -static int entire_flash_locked; - -/* The previous write protect state before sys jump */ - -struct flash_wp_state { - int entire_flash_locked; -}; - -/** - * Read from physical flash. - * - * @param offset Flash offset to write. - * @param size Number of bytes to write. - * @param data Destination buffer for data. - */ -int crec_flash_physical_read(int offset, int size, char *data) -{ - return spi_flash_read(data, offset, size); -} - -/** - * Write to physical flash. - * - * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE. - * - * @param offset Flash offset to write. - * @param size Number of bytes to write. - * @param data Data to write to flash. Must be 32-bit aligned. - */ -int crec_flash_physical_write(int offset, int size, const char *data) -{ - int ret = EC_SUCCESS; - int i, write_size; - - if (entire_flash_locked) - return EC_ERROR_ACCESS_DENIED; - - /* Fail if offset, size, and data aren't at least word-aligned */ - if ((offset | size | (uint32_t)(uintptr_t)data) & 3) - return EC_ERROR_INVAL; - - for (i = 0; i < size; i += write_size) { - write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE); - ret = spi_flash_write(offset + i, write_size, - (uint8_t *)data + i); - if (ret != EC_SUCCESS) - break; - } - return ret; -} - -/** - * Erase physical flash. - * - * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE. - * - * @param offset Flash offset to erase. - * @param size Number of bytes to erase. - */ -int crec_flash_physical_erase(int offset, int size) -{ - int ret; - - if (entire_flash_locked) - return EC_ERROR_ACCESS_DENIED; - - ret = spi_flash_erase(offset, size); - return ret; -} - -/** - * Read physical write protect setting for a flash bank. - * - * @param bank Bank index to check. - * @return non-zero if bank is protected until reboot. - */ -int crec_flash_physical_get_protect(int bank) -{ - return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE, - CONFIG_FLASH_BANK_SIZE); -} - -/** - * Protect flash now. - * - * This is always successful, and only emulates "now" protection - * - * @param all Protect all (=1) or just read-only - * @return non-zero if error. - */ -int crec_flash_physical_protect_now(int all) -{ - if (all) - entire_flash_locked = 1; - - /* - * RO "now" protection is not currently implemented. If needed, it - * can be added by splitting the entire_flash_locked variable into - * and RO and RW vars, and setting + checking the appropriate var - * as required. - */ - return EC_SUCCESS; -} - -/** - * Return flash protect state flags from the physical layer. - * - * This should only be called by flash_get_protect(). - * - * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h - */ -uint32_t crec_flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - - if (spi_flash_check_protect(CONFIG_WP_STORAGE_OFF, - CONFIG_WP_STORAGE_SIZE)) { - flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW; - } - - if (entire_flash_locked) - flags |= EC_FLASH_PROTECT_ALL_NOW; - - return flags; -} - -/** - * Return the valid flash protect flags. - * - * @return A combination of EC_FLASH_PROTECT_* flags from ec_commands.h - */ -uint32_t crec_flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; -} - -/** - * Return the writable flash protect flags. - * - * @param cur_flags The current flash protect flags. - * @return A combination of EC_FLASH_PROTECT_* flags from ec_commands.h - */ -uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - enum spi_flash_wp wp_status = SPI_WP_NONE; - - wp_status = spi_flash_check_wp(); - - if (wp_status == SPI_WP_NONE || - (wp_status == SPI_WP_HARDWARE && - !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))) - ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW; - - if (!entire_flash_locked) - ret |= EC_FLASH_PROTECT_ALL_NOW; - - return ret; -} - -/** - * Enable write protect for the specified range. - * - * Once write protect is enabled, it will stay enabled until HW PIN is - * de-asserted and SRP register is unset. - * - * However, this implementation treats EC_FLASH_PROTECT_ALL_AT_BOOT as - * EC_FLASH_PROTECT_RO_AT_BOOT but tries to remember if "all" region - * is protected. - * - * @param new_flags to protect (only EC_FLASH_PROTECT_*_AT_BOOT are - * taken care of) - * @return EC_SUCCESS, or nonzero if error. - */ -int crec_flash_physical_protect_at_boot(uint32_t new_flags) -{ - int offset, size, ret; - enum spi_flash_wp flashwp = SPI_WP_NONE; - - if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) { - /* Clear protection */ - offset = size = 0; - flashwp = SPI_WP_NONE; - } else { - if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) - entire_flash_locked = 1; - - offset = CONFIG_WP_STORAGE_OFF; - size = CONFIG_WP_STORAGE_SIZE; - flashwp = SPI_WP_HARDWARE; - } - - ret = spi_flash_set_protect(offset, size); - if (ret == EC_SUCCESS) - ret = spi_flash_set_wp(flashwp); - return ret; -} - -/** - * Initialize the module. - * - * Applies at-boot protection settings if necessary. - */ -int crec_flash_pre_init(void) -{ - crec_flash_physical_restore_state(); - return EC_SUCCESS; -} - -int crec_flash_physical_restore_state(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - int version, size; - const struct flash_wp_state *prev; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) { - prev = (const struct flash_wp_state *)system_get_jump_tag( - FLASH_SYSJUMP_TAG, &version, &size); - if (prev && version == FLASH_HOOK_VERSION && - size == sizeof(*prev)) - entire_flash_locked = prev->entire_flash_locked; - return 1; - } - - return 0; -} - -/*****************************************************************************/ -/* Hooks */ - -static void flash_preserve_state(void) -{ - struct flash_wp_state state; - - state.entire_flash_locked = entire_flash_locked; - - system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION, - sizeof(state), &state); -} -DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT); diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c deleted file mode 100644 index 09b0895376..0000000000 --- a/chip/mec1322/gpio.c +++ /dev/null @@ -1,287 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for MEC1322 */ - -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -struct gpio_int_mapping { - int8_t girq_id; - int8_t port_offset; -}; - -/* Mapping from GPIO port to GIRQ info */ -static const struct gpio_int_mapping int_map[22] = { - { 11, 0 }, { 11, 0 }, { 11, 0 }, { 11, 0 }, { 10, 4 }, { 10, 4 }, - { 10, 4 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { 9, 10 }, { 9, 10 }, - { 9, 10 }, { 9, 10 }, { 8, 14 }, { 8, 14 }, { 8, 14 }, { -1, -1 }, - { -1, -1 }, { -1, -1 }, { 20, 20 }, { 20, 20 } -}; - -void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) -{ - int i; - uint32_t val; - - while (mask) { - i = __builtin_ffs(mask) - 1; - val = MEC1322_GPIO_CTL(port, i); - val &= ~(BIT(12) | BIT(13)); - /* mux_control = DEFAULT, indicates GPIO */ - if (func > GPIO_ALT_FUNC_DEFAULT) - val |= (func & 0x3) << 12; - MEC1322_GPIO_CTL(port, i) = val; - mask &= ~BIT(i); - } -} - -test_mockable int gpio_get_level(enum gpio_signal signal) -{ - uint32_t mask = gpio_list[signal].mask; - int i; - uint32_t val; - - if (mask == 0) - return 0; - i = GPIO_MASK_TO_NUM(mask); - val = MEC1322_GPIO_CTL(gpio_list[signal].port, i); - - return (val & BIT(24)) ? 1 : 0; -} - -void gpio_set_level(enum gpio_signal signal, int value) -{ - uint32_t mask = gpio_list[signal].mask; - int i; - - if (mask == 0) - return; - i = GPIO_MASK_TO_NUM(mask); - - if (value) - MEC1322_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16); - else - MEC1322_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16); -} - -void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) -{ - int i; - uint32_t val; - while (mask) { - i = GPIO_MASK_TO_NUM(mask); - mask &= ~BIT(i); - val = MEC1322_GPIO_CTL(port, i); - - /* - * Select open drain first, so that we don't glitch the signal - * when changing the line to an output. - */ - if (flags & GPIO_OPEN_DRAIN) - val |= BIT(8); - else - val &= ~BIT(8); - - if (flags & GPIO_OUTPUT) { - val |= BIT(9); - val &= ~BIT(10); - } else { - val &= ~BIT(9); - val |= BIT(10); - } - - /* Handle pullup / pulldown */ - if (flags & GPIO_PULL_UP) - val = (val & ~0x3) | 0x1; - else if (flags & GPIO_PULL_DOWN) - val = (val & ~0x3) | 0x2; - else - val &= ~0x3; - - /* Set up interrupt */ - if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) - val |= BIT(7); - else - val &= ~BIT(7); - - val &= ~(0x7 << 4); - - if ((flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) - val |= 0x7 << 4; - else if (flags & GPIO_INT_F_RISING) - val |= 0x5 << 4; - else if (flags & GPIO_INT_F_FALLING) - val |= 0x6 << 4; - else if (flags & GPIO_INT_F_HIGH) - val |= 0x1 << 4; - else if (!(flags & GPIO_INT_F_LOW)) /* No interrupt flag set */ - val |= 0x4 << 4; - - /* Set up level */ - if (flags & GPIO_HIGH) - val |= BIT(16); - else if (flags & GPIO_LOW) - val &= ~BIT(16); - - MEC1322_GPIO_CTL(port, i) = val; - } -} - -int gpio_enable_interrupt(enum gpio_signal signal) -{ - int i, port, girq_id, bit_id; - - if (gpio_list[signal].mask == 0) - return EC_SUCCESS; - - i = GPIO_MASK_TO_NUM(gpio_list[signal].mask); - port = gpio_list[signal].port; - girq_id = int_map[port].girq_id; - bit_id = (port - int_map[port].port_offset) * 8 + i; - - MEC1322_INT_ENABLE(girq_id) |= BIT(bit_id); - MEC1322_INT_BLK_EN |= BIT(girq_id); - - return EC_SUCCESS; -} - -int gpio_disable_interrupt(enum gpio_signal signal) -{ - int i, port, girq_id, bit_id; - - if (gpio_list[signal].mask == 0) - return EC_SUCCESS; - - i = GPIO_MASK_TO_NUM(gpio_list[signal].mask); - port = gpio_list[signal].port; - girq_id = int_map[port].girq_id; - bit_id = (port - int_map[port].port_offset) * 8 + i; - - MEC1322_INT_DISABLE(girq_id) = BIT(bit_id); - - return EC_SUCCESS; -} - -int gpio_clear_pending_interrupt(enum gpio_signal signal) -{ - int i, port, girq_id, bit_id; - - if (gpio_list[signal].mask == 0) - return EC_SUCCESS; - - i = GPIO_MASK_TO_NUM(gpio_list[signal].mask); - port = gpio_list[signal].port; - girq_id = int_map[port].girq_id; - bit_id = (port - int_map[port].port_offset) * 8 + i; - - /* Clear interrupt source sticky status bit even if not enabled */ - MEC1322_INT_SOURCE(girq_id) |= 1 << bit_id; - - return EC_SUCCESS; -} - -void gpio_pre_init(void) -{ - int i; - int flags; - int is_warm = system_is_reboot_warm(); - const struct gpio_info *g = gpio_list; - - for (i = 0; i < GPIO_COUNT; i++, g++) { - flags = g->flags; - - if (flags & GPIO_DEFAULT) - continue; - - /* - * If this is a warm reboot, don't set the output levels or - * we'll shut off the AP. - */ - if (is_warm) - flags &= ~(GPIO_LOW | GPIO_HIGH); - - gpio_set_flags_by_mask(g->port, g->mask, flags); - - /* Use as GPIO, not alternate function */ - gpio_set_alternate_function(g->port, g->mask, - GPIO_ALT_FUNC_NONE); - } -} - -/* Clear any interrupt flags before enabling GPIO interrupt */ -#define ENABLE_GPIO_GIRQ(x) \ - do { \ - MEC1322_INT_SOURCE(x) |= MEC1322_INT_RESULT(x); \ - task_enable_irq(MEC1322_IRQ_GIRQ##x); \ - } while (0) - -static void gpio_init(void) -{ - ENABLE_GPIO_GIRQ(8); - ENABLE_GPIO_GIRQ(9); - ENABLE_GPIO_GIRQ(10); - ENABLE_GPIO_GIRQ(11); - ENABLE_GPIO_GIRQ(20); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -/*****************************************************************************/ -/* Interrupt handlers */ - -/** - * Handler for each GIRQ interrupt. This reads and clears the interrupt bits for - * the GIRQ interrupt, then finds and calls the corresponding GPIO interrupt - * handlers. - * - * @param girq GIRQ index - * @param port_offset GPIO port offset for the given GIRQ - */ -static void gpio_interrupt(int girq, int port_offset) -{ - int i, bit; - const struct gpio_info *g = gpio_list; - uint32_t sts = MEC1322_INT_RESULT(girq); - - MEC1322_INT_SOURCE(girq) |= sts; - - for (i = 0; i < GPIO_IH_COUNT && sts; ++i, ++g) { - bit = (g->port - port_offset) * 8 + __builtin_ffs(g->mask) - 1; - if (sts & BIT(bit)) - gpio_irq_handlers[i](i); - sts &= ~BIT(bit); - } -} - -#define GPIO_IRQ_FUNC(irqfunc, girq, port_offset) \ - static void irqfunc(void) \ - { \ - gpio_interrupt(girq, port_offset); \ - } - -GPIO_IRQ_FUNC(__girq_8_interrupt, 8, 14); -GPIO_IRQ_FUNC(__girq_9_interrupt, 9, 10); -GPIO_IRQ_FUNC(__girq_10_interrupt, 10, 4); -GPIO_IRQ_FUNC(__girq_11_interrupt, 11, 0); -GPIO_IRQ_FUNC(__girq_20_interrupt, 20, 20); - -#undef GPIO_IRQ_FUNC - -/* - * Declare IRQs. Nesting this macro inside the GPIO_IRQ_FUNC macro works - * poorly because DECLARE_IRQ() stringizes its inputs. - */ -DECLARE_IRQ(MEC1322_IRQ_GIRQ8, __girq_8_interrupt, 1); -DECLARE_IRQ(MEC1322_IRQ_GIRQ9, __girq_9_interrupt, 1); -DECLARE_IRQ(MEC1322_IRQ_GIRQ10, __girq_10_interrupt, 1); -DECLARE_IRQ(MEC1322_IRQ_GIRQ11, __girq_11_interrupt, 1); -DECLARE_IRQ(MEC1322_IRQ_GIRQ20, __girq_20_interrupt, 1); diff --git a/chip/mec1322/hwtimer.c b/chip/mec1322/hwtimer.c deleted file mode 100644 index 7f2d643d98..0000000000 --- a/chip/mec1322/hwtimer.c +++ /dev/null @@ -1,114 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hardware timers driver */ - -#include "clock.h" -#include "common.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "task.h" -#include "timer.h" - -void __hw_clock_event_set(uint32_t deadline) -{ - MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) - (0xffffffff - deadline); - MEC1322_TMR32_CTL(1) |= BIT(5); -} - -uint32_t __hw_clock_event_get(void) -{ - return MEC1322_TMR32_CNT(1) - MEC1322_TMR32_CNT(0) + 0xffffffff; -} - -void __hw_clock_event_clear(void) -{ - MEC1322_TMR32_CTL(1) &= ~BIT(5); -} - -uint32_t __hw_clock_source_read(void) -{ - return 0xffffffff - MEC1322_TMR32_CNT(0); -} - -void __hw_clock_source_set(uint32_t ts) -{ - MEC1322_TMR32_CTL(0) &= ~BIT(5); - MEC1322_TMR32_CNT(0) = 0xffffffff - ts; - MEC1322_TMR32_CTL(0) |= BIT(5); -} - -static void __hw_clock_source_irq(int timer_id) -{ - if (timer_id == 1) - MEC1322_TMR32_STS(1) |= 1; - /* If IRQ is from timer 0, 32-bit timer overflowed */ - process_timers(timer_id == 0); -} - -static void __hw_clock_source_irq_0(void) -{ - __hw_clock_source_irq(0); -} -DECLARE_IRQ(MEC1322_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1); -static void __hw_clock_source_irq_1(void) -{ - __hw_clock_source_irq(1); -} -DECLARE_IRQ(MEC1322_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1); - -static void configure_timer(int timer_id) -{ - uint32_t val; - - /* Ensure timer is not running */ - MEC1322_TMR32_CTL(timer_id) &= ~BIT(5); - - /* Enable timer */ - MEC1322_TMR32_CTL(timer_id) |= BIT(0); - - val = MEC1322_TMR32_CTL(timer_id); - - /* Pre-scale = 48 -> 1MHz -> Period = 1us */ - val = (val & 0xffff) | (47 << 16); - - MEC1322_TMR32_CTL(timer_id) = val; - - /* Set preload to use the full 32 bits of the timer */ - MEC1322_TMR32_PRE(timer_id) = 0xffffffff; - - /* Enable interrupt */ - MEC1322_TMR32_IEN(timer_id) |= 1; -} - -int __hw_clock_source_init(uint32_t start_t) -{ - /* - * The timer can only fire interrupt when its value reaches zero. - * Therefore we need two timers: - * - Timer 0 as free running timer - * - Timer 1 as event timer - */ - configure_timer(0); - configure_timer(1); - - /* Override the count */ - MEC1322_TMR32_CNT(0) = 0xffffffff - start_t; - - /* Auto restart */ - MEC1322_TMR32_CTL(0) |= BIT(3); - - /* Start counting in timer 0 */ - MEC1322_TMR32_CTL(0) |= BIT(5); - - /* Enable interrupt */ - task_enable_irq(MEC1322_IRQ_TIMER32_0); - task_enable_irq(MEC1322_IRQ_TIMER32_1); - MEC1322_INT_ENABLE(23) |= BIT(4) | BIT(5); - MEC1322_INT_BLK_EN |= BIT(23); - - return MEC1322_IRQ_TIMER32_1; -} diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c deleted file mode 100644 index 5068aff978..0000000000 --- a/chip/mec1322/i2c.c +++ /dev/null @@ -1,532 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* I2C port module for MEC1322 */ - -#include "builtin/assert.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) - -#define I2C_CLOCK 16000000 /* 16 MHz */ - -/* Status */ -#define STS_NBB BIT(0) /* Bus busy */ -#define STS_LAB BIT(1) /* Arbitration lost */ -#define STS_LRB BIT(3) /* Last received bit */ -#define STS_BER BIT(4) /* Bus error */ -#define STS_PIN BIT(7) /* Pending interrupt */ - -/* Control */ -#define CTRL_ACK BIT(0) /* Acknowledge */ -#define CTRL_STO BIT(1) /* STOP */ -#define CTRL_STA BIT(2) /* START */ -#define CTRL_ENI BIT(3) /* Enable interrupt */ -#define CTRL_ESO BIT(6) /* Enable serial output */ -#define CTRL_PIN BIT(7) /* Pending interrupt not */ - -/* Completion */ -#define COMP_IDLE BIT(29) /* i2c bus is idle */ -#define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */ - -/* Maximum transfer of a SMBUS block transfer */ -#define SMBUS_MAX_BLOCK_SIZE 32 - -/* - * Amount of time to blocking wait for i2c bus to finish. After this blocking - * timeout, if the bus is still not finished, then allow other tasks to run. - * Note: this is just long enough for a 400kHz bus to finish transmitting one - * byte assuming the bus isn't being held. - */ -#define I2C_WAIT_BLOCKING_TIMEOUT_US 25 - -enum i2c_transaction_state { - /* Stop condition was sent in previous transaction */ - I2C_TRANSACTION_STOPPED, - /* Stop condition was not sent in previous transaction */ - I2C_TRANSACTION_OPEN, -}; - -/* I2C controller state data */ -static struct { - /* Transaction timeout, or 0 to use default. */ - uint32_t timeout_us; - /* Task waiting on port, or TASK_ID_INVALID if none. */ - volatile task_id_t task_waiting; - enum i2c_transaction_state transaction_state; -} cdata[I2C_CONTROLLER_COUNT]; - -/* Map port number to port name in datasheet, for debug prints. */ -static const char *i2c_port_names[MEC1322_I2C_PORT_COUNT] = { - [MEC1322_I2C0_0] = "0_0", [MEC1322_I2C0_1] = "0_1", - [MEC1322_I2C1] = "1", [MEC1322_I2C2] = "2", - [MEC1322_I2C3] = "3", -}; - -static void configure_controller_speed(int controller, int kbps) -{ - int t_low, t_high; - const int period = I2C_CLOCK / 1000 / kbps; - - /* - * Refer to NXP UM10204 for minimum timing requirement of T_Low and - * T_High. - * http://www.nxp.com/documents/user_manual/UM10204.pdf - */ - if (kbps > 400) { - /* Fast mode plus */ - t_low = t_high = period / 2 - 1; - MEC1322_I2C_DATA_TIM(controller) = 0x06060601; - MEC1322_I2C_DATA_TIM_2(controller) = 0x06; - } else if (kbps > 100) { - /* Fast mode */ - /* By spec, clk low period is 1.3us min */ - t_low = MAX((int)(I2C_CLOCK * 1.3 / 1000000), period / 2 - 1); - t_high = period - t_low - 2; - MEC1322_I2C_DATA_TIM(controller) = 0x040a0a01; - MEC1322_I2C_DATA_TIM_2(controller) = 0x0a; - } else { - /* Standard mode */ - t_low = t_high = period / 2 - 1; - MEC1322_I2C_DATA_TIM(controller) = 0x0c4d5006; - MEC1322_I2C_DATA_TIM_2(controller) = 0x4d; - } - - /* Clock periods is one greater than the contents of these fields */ - MEC1322_I2C_BUS_CLK(controller) = ((t_high & 0xff) << 8) | - (t_low & 0xff); -} - -static void configure_controller(int controller, int kbps) -{ - MEC1322_I2C_CTRL(controller) = CTRL_PIN; - MEC1322_I2C_OWN_ADDR(controller) = 0x0; - configure_controller_speed(controller, kbps); - MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | CTRL_ACK | - CTRL_ENI; - MEC1322_I2C_CONFIG(controller) |= BIT(10); /* ENAB */ - - /* Enable interrupt */ - MEC1322_I2C_CONFIG(controller) |= BIT(29); /* ENIDI */ - MEC1322_INT_ENABLE(12) |= BIT(controller); - MEC1322_INT_BLK_EN |= BIT(12); -} - -static void reset_controller(int controller) -{ - int i; - - MEC1322_I2C_CONFIG(controller) |= BIT(9); - udelay(100); - MEC1322_I2C_CONFIG(controller) &= ~BIT(9); - - for (i = 0; i < i2c_ports_used; ++i) - if (controller == i2c_port_to_controller(i2c_ports[i].port)) { - configure_controller(controller, i2c_ports[i].kbps); - cdata[controller].transaction_state = - I2C_TRANSACTION_STOPPED; - break; - } -} - -static int wait_for_interrupt(int controller, int timeout) -{ - int event; - - if (timeout <= 0) - return EC_ERROR_TIMEOUT; - - cdata[controller].task_waiting = task_get_current(); - task_enable_irq(MEC1322_IRQ_I2C_0 + controller); - - /* Wait until I2C interrupt or timeout. */ - event = task_wait_event_mask(TASK_EVENT_I2C_IDLE, timeout); - - task_disable_irq(MEC1322_IRQ_I2C_0 + controller); - cdata[controller].task_waiting = TASK_ID_INVALID; - - return (event & TASK_EVENT_TIMER) ? EC_ERROR_TIMEOUT : EC_SUCCESS; -} - -static int wait_idle(int controller) -{ - uint8_t sts = MEC1322_I2C_STATUS(controller); - uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US; - uint64_t task_timeout = block_timeout + cdata[controller].timeout_us; - int rv = 0; - - while (!(sts & STS_NBB)) { - if (rv) - return rv; - if (get_time().val > block_timeout) - rv = wait_for_interrupt(controller, - task_timeout - get_time().val); - sts = MEC1322_I2C_STATUS(controller); - } - - if (sts & (STS_BER | STS_LAB)) - return EC_ERROR_UNKNOWN; - return EC_SUCCESS; -} - -static int wait_byte_done(int controller) -{ - uint8_t sts = MEC1322_I2C_STATUS(controller); - uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US; - uint64_t task_timeout = block_timeout + cdata[controller].timeout_us; - int rv = 0; - - while (sts & STS_PIN) { - if (rv) - return rv; - if (get_time().val > block_timeout) - rv = wait_for_interrupt(controller, - task_timeout - get_time().val); - sts = MEC1322_I2C_STATUS(controller); - } - - return sts & STS_LRB; -} - -static void select_port(int port) -{ - /* - * I2C0_1 uses port 1 of controller 0. All other I2C pin sets - * use port 0. - */ - uint8_t port_sel = (port == MEC1322_I2C0_1) ? 1 : 0; - int controller = i2c_port_to_controller(port); - - MEC1322_I2C_CONFIG(controller) &= ~0xf; - MEC1322_I2C_CONFIG(controller) |= port_sel; -} - -static inline int get_line_level(int controller) -{ - int ret, ctrl; - /* - * We need to enable BB (Bit Bang) mode in order to read line level - * properly, othervise line levels return always idle (0x60). - */ - ctrl = MEC1322_I2C_BB_CTRL(controller); - MEC1322_I2C_BB_CTRL(controller) |= 1; - ret = (MEC1322_I2C_BB_CTRL(controller) >> 5) & 0x3; - MEC1322_I2C_BB_CTRL(controller) = ctrl; - return ret; -} - -static inline void push_in_buf(uint8_t **in, uint8_t val, int skip) -{ - if (!skip) { - **in = val; - (*in)++; - } -} - -int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, - int out_size, uint8_t *in, int in_size, int flags) -{ - int i; - int controller; - int send_start = flags & I2C_XFER_START; - int send_stop = flags & I2C_XFER_STOP; - int skip = 0; - int bytes_to_read; - uint8_t reg; - int ret_done; - - if (out_size == 0 && in_size == 0) - return EC_SUCCESS; - - select_port(port); - controller = i2c_port_to_controller(port); - if (send_start && - cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED) - wait_idle(controller); - - reg = MEC1322_I2C_STATUS(controller); - if (send_start && - cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED && - (((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB)) || - (get_line_level(controller) != I2C_LINE_IDLE))) { - CPRINTS("i2c%s bad status 0x%02x, SCL=%d, SDA=%d", - i2c_port_names[port], reg, - get_line_level(controller) & I2C_LINE_SCL_HIGH, - get_line_level(controller) & I2C_LINE_SDA_HIGH); - - /* Attempt to unwedge the port. */ - i2c_unwedge(port); - - /* Bus error, bus busy, or arbitration lost. Try reset. */ - reset_controller(controller); - select_port(port); - - /* - * We don't know what edges the slave saw, so sleep long enough - * that the slave will see the new start condition below. - */ - usleep(1000); - } - - if (out_size) { - if (send_start) { - MEC1322_I2C_DATA(controller) = - (uint8_t)(I2C_STRIP_FLAGS(addr_flags) << 1); - - /* Clock out the slave address, sending START bit */ - MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | - CTRL_ENI | CTRL_ACK | - CTRL_STA; - cdata[controller].transaction_state = - I2C_TRANSACTION_OPEN; - } - - for (i = 0; i < out_size; ++i) { - ret_done = wait_byte_done(controller); - if (ret_done) - goto err_chip_i2c_xfer; - MEC1322_I2C_DATA(controller) = out[i]; - } - ret_done = wait_byte_done(controller); - if (ret_done) - goto err_chip_i2c_xfer; - - /* - * Send STOP bit if the stop flag is on, and caller - * doesn't expect to receive data. - */ - if (send_stop && in_size == 0) { - MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | - CTRL_STO | CTRL_ACK; - cdata[controller].transaction_state = - I2C_TRANSACTION_STOPPED; - } - } - - if (in_size) { - /* Resend start bit when changing direction */ - if (out_size || send_start) { - /* Repeated start case */ - if (cdata[controller].transaction_state == - I2C_TRANSACTION_OPEN) - MEC1322_I2C_CTRL(controller) = - CTRL_ESO | CTRL_STA | CTRL_ACK | - CTRL_ENI; - - MEC1322_I2C_DATA(controller) = - (uint8_t)(I2C_STRIP_FLAGS(addr_flags) << 1) | - 0x01; - - /* New transaction case, clock out slave address. */ - if (cdata[controller].transaction_state == - I2C_TRANSACTION_STOPPED) - MEC1322_I2C_CTRL(controller) = - CTRL_ESO | CTRL_STA | CTRL_ACK | - CTRL_ENI | CTRL_PIN; - - cdata[controller].transaction_state = - I2C_TRANSACTION_OPEN; - - /* Skip over the unused byte */ - skip = 1; - in_size++; - } - - /* Special flags need to be set for last two bytes */ - bytes_to_read = send_stop ? in_size - 2 : in_size; - - for (i = 0; i < bytes_to_read; ++i) { - ret_done = wait_byte_done(controller); - if (ret_done) - goto err_chip_i2c_xfer; - push_in_buf(&in, MEC1322_I2C_DATA(controller), skip); - skip = 0; - } - ret_done = wait_byte_done(controller); - if (ret_done) - goto err_chip_i2c_xfer; - - if (send_stop) { - /* - * De-assert ACK bit before reading the next to last - * byte, so that the last byte is NACK'ed. - */ - MEC1322_I2C_CTRL(controller) = CTRL_ESO | CTRL_ENI; - push_in_buf(&in, MEC1322_I2C_DATA(controller), skip); - ret_done = wait_byte_done(controller); - if (ret_done) - goto err_chip_i2c_xfer; - - /* Send STOP */ - MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | - CTRL_ACK | CTRL_STO; - - cdata[controller].transaction_state = - I2C_TRANSACTION_STOPPED; - - /* - * We need to know our stop point two bytes in - * advance. If we don't know soon enough, we need - * to do an extra read (to last_addr + 1) to - * issue the stop. - */ - push_in_buf(&in, MEC1322_I2C_DATA(controller), - in_size == 1); - } - } - - /* Check for error conditions */ - if (MEC1322_I2C_STATUS(controller) & (STS_LAB | STS_BER)) - return EC_ERROR_UNKNOWN; - - return EC_SUCCESS; -err_chip_i2c_xfer: - /* Send STOP and return error */ - MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | CTRL_STO | - CTRL_ACK; - cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED; - if (ret_done == STS_LRB) - return EC_ERROR_BUSY; - else if (ret_done == EC_ERROR_TIMEOUT) { - /* - * If our transaction timed out then our i2c controller - * may be wedged without showing any other outward signs - * of failure. Reset the controller so that future - * transactions have a chance of success. - */ - reset_controller(controller); - return EC_ERROR_TIMEOUT; - } else - return EC_ERROR_UNKNOWN; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS) - return 1; - - return gpio_get_level(g); -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - /* If no SDA pin defined for this port, then return 1 to appear idle. */ - if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS) - return 1; - - return gpio_get_level(g); -} - -int i2c_get_line_levels(int port) -{ - int rv; - - i2c_lock(port, 1); - select_port(port); - rv = get_line_level(i2c_port_to_controller(port)); - i2c_lock(port, 0); - return rv; -} - -int i2c_port_to_controller(int port) -{ - if (port < 0 || port >= MEC1322_I2C_PORT_COUNT) - return -1; - return (port == MEC1322_I2C0_0) ? 0 : port - 1; -} - -void i2c_set_timeout(int port, uint32_t timeout) -{ - /* Param is port, but timeout is stored by-controller. */ - cdata[i2c_port_to_controller(port)].timeout_us = - timeout ? timeout : I2C_TIMEOUT_DEFAULT_US; -} - -void i2c_init(void) -{ - int i; - int controller; - int controller0_kbps = -1; - - /* Configure GPIOs */ - gpio_config_module(MODULE_I2C, 1); - - for (i = 0; i < i2c_ports_used; ++i) { - /* - * If this controller has multiple ports, check if we already - * configured it. If so, ensure previously configured bitrate - * matches. - */ - controller = i2c_port_to_controller(i2c_ports[i].port); - if (controller == 0) { - if (controller0_kbps != -1) { - ASSERT(controller0_kbps == i2c_ports[i].kbps); - continue; - } - controller0_kbps = i2c_ports[i].kbps; - } - configure_controller(controller, i2c_ports[i].kbps); - cdata[controller].task_waiting = TASK_ID_INVALID; - cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED; - - /* Use default timeout. */ - i2c_set_timeout(i2c_ports[i].port, 0); - } -} - -static void handle_interrupt(int controller) -{ - int id = cdata[controller].task_waiting; - - /* Clear the interrupt status */ - MEC1322_I2C_COMPLETE(controller) &= (COMP_RW_BITS_MASK | COMP_IDLE); - - /* - * Write to control register interferes with I2C transaction. - * Instead, let's disable IRQ from the core until the next time - * we want to wait for STS_PIN/STS_NBB. - */ - task_disable_irq(MEC1322_IRQ_I2C_0 + controller); - - /* Wake up the task which was waiting on the I2C interrupt, if any. */ - if (id != TASK_ID_INVALID) - task_set_event(id, TASK_EVENT_I2C_IDLE); -} - -static void i2c0_interrupt(void) -{ - handle_interrupt(0); -} -static void i2c1_interrupt(void) -{ - handle_interrupt(1); -} -static void i2c2_interrupt(void) -{ - handle_interrupt(2); -} -static void i2c3_interrupt(void) -{ - handle_interrupt(3); -} - -DECLARE_IRQ(MEC1322_IRQ_I2C_0, i2c0_interrupt, 2); -DECLARE_IRQ(MEC1322_IRQ_I2C_1, i2c1_interrupt, 2); -DECLARE_IRQ(MEC1322_IRQ_I2C_2, i2c2_interrupt, 2); -DECLARE_IRQ(MEC1322_IRQ_I2C_3, i2c3_interrupt, 2); diff --git a/chip/mec1322/keyboard_raw.c b/chip/mec1322/keyboard_raw.c deleted file mode 100644 index 67200b6c04..0000000000 --- a/chip/mec1322/keyboard_raw.c +++ /dev/null @@ -1,88 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Raw keyboard I/O layer for MEC1322 - */ - -#include "gpio.h" -#include "keyboard_config.h" -#include "keyboard_raw.h" -#include "keyboard_scan.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void keyboard_raw_init(void) -{ - keyboard_raw_enable_interrupt(0); - gpio_config_module(MODULE_KEYBOARD_SCAN, 1); - - /* Enable keyboard scan interrupt */ - MEC1322_INT_ENABLE(17) |= BIT(21); - MEC1322_INT_BLK_EN |= BIT(17); - MEC1322_KS_KSI_INT_EN = 0xff; -} - -void keyboard_raw_task_start(void) -{ - task_enable_irq(MEC1322_IRQ_KSC_INT); -} - -test_mockable void keyboard_raw_drive_column(int out) -{ - if (out == KEYBOARD_COLUMN_ALL) { - MEC1322_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */ -#ifdef CONFIG_KEYBOARD_COL2_INVERTED - gpio_set_level(GPIO_KBD_KSO2, 1); -#endif - } else if (out == KEYBOARD_COLUMN_NONE) { - MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */ -#ifdef CONFIG_KEYBOARD_COL2_INVERTED - gpio_set_level(GPIO_KBD_KSO2, 0); -#endif - } else { -#ifdef CONFIG_KEYBOARD_COL2_INVERTED - if (out == 2) { - MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */ - gpio_set_level(GPIO_KBD_KSO2, 1); - } else { - MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE; - gpio_set_level(GPIO_KBD_KSO2, 0); - } -#else - MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE; -#endif - } -} - -test_mockable int keyboard_raw_read_rows(void) -{ - /* Invert it so 0=not pressed, 1=pressed */ - return (MEC1322_KS_KSI_INPUT & 0xff) ^ 0xff; -} - -void keyboard_raw_enable_interrupt(int enable) -{ - if (enable) { - task_clear_pending_irq(MEC1322_IRQ_KSC_INT); - task_enable_irq(MEC1322_IRQ_KSC_INT); - } else { - task_disable_irq(MEC1322_IRQ_KSC_INT); - } -} - -static void keyboard_raw_interrupt(void) -{ - /* Clear interrupt status bits */ - MEC1322_KS_KSI_STATUS = 0xff; - - /* Wake keyboard scan task to handle interrupt */ - task_wake(TASK_ID_KEYSCAN); -} -DECLARE_IRQ(MEC1322_IRQ_KSC_INT, keyboard_raw_interrupt, 1); - -int keyboard_raw_is_input_low(int port, int id) -{ - return (MEC1322_GPIO_CTL(port, id) & BIT(24)) == 0; -} diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c deleted file mode 100644 index 92d3d2facc..0000000000 --- a/chip/mec1322/lfw/ec_lfw.c +++ /dev/null @@ -1,272 +0,0 @@ -/* Copyright 2015 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * MEC1322 SoC little FW - * - */ - -#include <stdint.h> - -#include "config.h" -#include "cros_version.h" -#include "gpio.h" -#include "spi.h" -#include "spi_flash.h" -#include "util.h" -#include "timer.h" -#include "dma.h" -#include "registers.h" -#include "cpu.h" -#include "clock.h" -#include "system.h" -#include "hwtimer.h" -#include "gpio_list.h" - -#include "ec_lfw.h" - -__attribute__((section(".intvector"))) -const struct int_vector_t hdr_int_vect = { - (void *)0x11FA00, /* init sp, unused, - set by MEC ROM loader*/ - &lfw_main, /* reset vector */ - &fault_handler, /* NMI handler */ - &fault_handler, /* HardFault handler */ - &fault_handler, /* MPU fault handler */ - &fault_handler /* Bus fault handler */ -}; - -/* SPI devices - from glados/board.c*/ -const struct spi_device_t spi_devices[] = { - { CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0 }, -}; -const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); - -void timer_init() -{ - uint32_t val = 0; - - /* Ensure timer is not running */ - MEC1322_TMR32_CTL(0) &= ~BIT(5); - - /* Enable timer */ - MEC1322_TMR32_CTL(0) |= BIT(0); - - val = MEC1322_TMR32_CTL(0); - - /* Pre-scale = 48 -> 1MHz -> Period = 1us */ - val = (val & 0xffff) | (47 << 16); - - MEC1322_TMR32_CTL(0) = val; - - /* Set preload to use the full 32 bits of the timer */ - MEC1322_TMR32_PRE(0) = 0xffffffff; - - /* Override the count */ - MEC1322_TMR32_CNT(0) = 0xffffffff; - - /* Auto restart */ - MEC1322_TMR32_CTL(0) |= BIT(3); - - /* Start counting in timer 0 */ - MEC1322_TMR32_CTL(0) |= BIT(5); -} - -static int spi_flash_readloc(uint8_t *buf_usr, unsigned int offset, - unsigned int bytes) -{ - uint8_t cmd[4] = { SPI_FLASH_READ, (offset >> 16) & 0xFF, - (offset >> 8) & 0xFF, offset & 0xFF }; - - if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) - return EC_ERROR_INVAL; - - return spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr, bytes); -} - -int spi_image_load(uint32_t offset) -{ - uint8_t *buf = - (uint8_t *)(CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE); - uint32_t i; - - BUILD_ASSERT(CONFIG_RO_SIZE == CONFIG_RW_SIZE); - memset((void *)buf, 0xFF, (CONFIG_RO_SIZE - 4)); - - for (i = 0; i < CONFIG_RO_SIZE; i += SPI_CHUNK_SIZE) - spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE); - - return 0; -} - -void udelay(unsigned us) -{ - uint32_t t0 = __hw_clock_source_read(); - while (__hw_clock_source_read() - t0 < us) - ; -} - -void usleep(unsigned us) -{ - udelay(us); -} - -int timestamp_expired(timestamp_t deadline, const timestamp_t *now) -{ - timestamp_t now_val; - - if (!now) { - now_val = get_time(); - now = &now_val; - } - - return now->le.lo >= deadline.le.lo; -} - -timestamp_t get_time(void) -{ - timestamp_t ts; - - ts.le.hi = 0; - ts.le.lo = __hw_clock_source_read(); - return ts; -} - -void uart_write_c(char c) -{ - /* Put in carriage return prior to newline to mimic uart_vprintf() */ - if (c == '\n') - uart_write_c('\r'); - - /* Wait for space in transmit FIFO. */ - while (!(MEC1322_UART_LSR & BIT(5))) - ; - MEC1322_UART_TB = c; -} - -void uart_puts(const char *str) -{ - if (!str || !*str) - return; - - do { - uart_write_c(*str++); - } while (*str); -} - -void fault_handler(void) -{ - uart_puts("EXCEPTION!\nTriggering watchdog reset\n"); - /* trigger reset in 1 ms */ - MEC1322_WDG_LOAD = 1; - MEC1322_WDG_CTL |= 1; - while (1) - ; -} - -void jump_to_image(uintptr_t init_addr) -{ - void (*resetvec)(void) = (void (*)(void))init_addr; - resetvec(); -} - -void uart_init(void) -{ - /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MEC1322_UART_CFG &= ~BIT(1); - - /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ - - /* Set CLK_SRC = 0 */ - MEC1322_UART_CFG &= ~BIT(0); - - /* Set DLAB = 1 */ - MEC1322_UART_LCR |= BIT(7); - - /* PBRG0/PBRG1 */ - MEC1322_UART_PBRG0 = 1; - MEC1322_UART_PBRG1 = 0; - - /* Set DLAB = 0 */ - MEC1322_UART_LCR &= ~BIT(7); - - /* Set word length to 8-bit */ - MEC1322_UART_LCR |= BIT(0) | BIT(1); - - /* Enable FIFO */ - MEC1322_UART_FCR = BIT(0); - - /* Activate UART */ - MEC1322_UART_ACT |= BIT(0); - - gpio_config_module(MODULE_UART, 1); -} - -void system_init(void) -{ - uint32_t wdt_sts = MEC1322_VBAT_STS & MEC1322_VBAT_STS_WDT; - uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST & MEC1322_PWR_RST_STS_VCC1; - - if (rst_sts || wdt_sts) - MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = EC_IMAGE_RO; -} - -enum ec_image system_get_image_copy(void) -{ - return MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX); -} - -void lfw_main() -{ - uintptr_t init_addr; - - /* install vector table */ - *((uintptr_t *)0xe000ed08) = (uintptr_t)&hdr_int_vect; - - /* Use 48 MHz processor clock to power through boot */ - MEC1322_PCR_PROC_CLK_CTL = 1; - -#ifdef CONFIG_WATCHDOG - /* Reload watchdog which may be running in case of sysjump */ - MEC1322_WDG_KICK = 1; -#ifdef CONFIG_WATCHDOG_HELP - /* Stop aux timer */ - MEC1322_TMR16_CTL(0) &= ~1; -#endif -#endif - - timer_init(); - clock_init(); - cpu_init(); - dma_init(); - uart_init(); - system_init(); - spi_enable(SPI_FLASH_DEVICE, 1); - - uart_puts("littlefw "); - uart_puts(current_image_data.version); - uart_puts("\n"); - - switch (system_get_image_copy()) { - case EC_IMAGE_RW: - uart_puts("lfw-RW load\n"); - init_addr = CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE; - spi_image_load(CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF); - break; - case EC_IMAGE_RO: - uart_puts("lfw-RO load\n"); - spi_image_load(CONFIG_EC_PROTECTED_STORAGE_OFF + - CONFIG_RO_STORAGE_OFF); - /* fall through */ - default: - MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = EC_IMAGE_RO; - init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE; - } - - jump_to_image(*(uintptr_t *)(init_addr + 4)); - - /* should never get here */ - while (1) - ; -} diff --git a/chip/mec1322/lfw/ec_lfw.h b/chip/mec1322/lfw/ec_lfw.h deleted file mode 100644 index cdb0d1cc32..0000000000 --- a/chip/mec1322/lfw/ec_lfw.h +++ /dev/null @@ -1,23 +0,0 @@ -/* Copyright 2015 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * MEC1322 SoC little FW - * - */ - -#include <stdnoreturn.h> - -noreturn void lfw_main(void) __attribute__((naked)); -void fault_handler(void) __attribute__((naked)); - -struct int_vector_t { - void *stack_ptr; - void *reset_vector; - void *nmi; - void *hard_fault; - void *bus_fault; - void *usage_fault; -}; - -#define SPI_CHUNK_SIZE 1024 diff --git a/chip/mec1322/lfw/ec_lfw.ld b/chip/mec1322/lfw/ec_lfw.ld deleted file mode 100644 index be3d1dc768..0000000000 --- a/chip/mec1322/lfw/ec_lfw.ld +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright 2015 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * MEC1322 SoC little FW - * - */ - -/* Memory Spaces Definitions */ -MEMORY -{ - VECTOR(r ) : ORIGIN = 0x100000, LENGTH = 0x18 - SRAM (xrw) : ORIGIN = 0x100018, LENGTH = 0xBE8 -} - -/* - * ld does not allow mathematical expressions in ORIGIN/LENGTH, so check the - * values here. - */ -ASSERT(ORIGIN(VECTOR) + LENGTH(VECTOR) == ORIGIN(SRAM), "Invalid SRAM origin.") -ASSERT(LENGTH(VECTOR) + LENGTH(SRAM) == 0xC00, "Invalid VECTOR+SRAM length.") - -/* - * The entry point is informative, for debuggers and simulators, - * since the Cortex-M vector points to it anyway. - */ -ENTRY(lfw_main) - -/* Sections Definitions */ - -SECTIONS -{ - - /* - * The vector table goes first - */ - .intvector : - { - . = ALIGN(4); - KEEP(*(.intvector)) - } > VECTOR - - /* - * The program code is stored in the .text section, - * which goes to FLASH. - */ - - .text : - { - *(.text .text.*) /* all remaining code */ - *(.rodata .rodata.*) /* read-only data (constants) */ - } >SRAM - - . = ALIGN(4); - - /* Padding */ - - .fill : { - FILL(0xFF); - . = ORIGIN(SRAM) + LENGTH(SRAM) - 1; - BYTE(0xFF); /* emit at least a byte to make linker happy */ - } - - __image_size = LOADADDR(.text) + SIZEOF(.text) - ORIGIN(VECTOR); -} diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c deleted file mode 100644 index 7dc1d621af..0000000000 --- a/chip/mec1322/lpc.c +++ /dev/null @@ -1,518 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* LPC module for MEC1322 */ - -#include "acpi.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "keyboard_protocol.h" -#include "lpc.h" -#include "port80.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "chipset.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) - -static uint8_t mem_mapped[0x200] __attribute__((section(".bss.big_align"))); - -static struct host_packet lpc_packet; -static struct host_cmd_handler_args host_cmd_args; -static uint8_t host_cmd_flags; /* Flags from host command */ - -static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4); -static int init_done; - -static struct ec_lpc_host_args *const lpc_host_args = - (struct ec_lpc_host_args *)mem_mapped; - -static void keyboard_irq_assert(void) -{ -#ifdef CONFIG_KEYBOARD_IRQ_GPIO - /* - * Enforce signal-high for long enough for the signal to be pulled high - * by the external pullup resistor. This ensures the host will see the - * following falling edge, regardless of the line state before this - * function call. - */ - gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1); - udelay(4); - /* Generate a falling edge */ - gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0); - udelay(4); - - /* Set signal high, now that we've generated the edge */ - gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1); -#else - /* - * SERIRQ is automatically sent by KBC - */ -#endif -} - -/** - * Generate SMI pulse to the host chipset via GPIO. - * - * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is - * 60ns. If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse - * length >61us. Both are short enough and events are infrequent, so just - * delay for 65us. - */ -static void lpc_generate_smi(void) -{ - gpio_set_level(GPIO_PCH_SMI_L, 0); - udelay(65); - gpio_set_level(GPIO_PCH_SMI_L, 1); -} - -static void lpc_generate_sci(void) -{ -#ifdef CONFIG_SCI_GPIO - gpio_set_level(CONFIG_SCI_GPIO, 0); - udelay(65); - gpio_set_level(CONFIG_SCI_GPIO, 1); -#else - MEC1322_ACPI_PM_STS |= 1; - udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US); - MEC1322_ACPI_PM_STS &= ~1; -#endif -} - -/** - * Update the level-sensitive wake signal to the AP. - * - * @param wake_events Currently asserted wake events - */ -static void lpc_update_wake(host_event_t wake_events) -{ - /* - * Mask off power button event, since the AP gets that through a - * separate dedicated GPIO. - */ - wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON); - - /* Signal is asserted low when wake events is non-zero */ - gpio_set_level(GPIO_PCH_WAKE_L, !wake_events); -} - -uint8_t *lpc_get_memmap_range(void) -{ - return mem_mapped + 0x100; -} - -static uint8_t *lpc_get_hostcmd_data_range(void) -{ - return mem_mapped; -} - -/** - * Update the host event status. - * - * Sends a pulse if masked event status becomes non-zero: - * - SMI pulse via PCH_SMI_L GPIO - * - SCI pulse via PCH_SCI_L GPIO - */ -void lpc_update_host_event_status(void) -{ - int need_sci = 0; - int need_smi = 0; - - if (!init_done) - return; - - /* Disable LPC interrupt while updating status register */ - task_disable_irq(MEC1322_IRQ_ACPIEC0_IBF); - - if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) { - /* Only generate SMI for first event */ - if (!(MEC1322_ACPI_EC_STATUS(0) & EC_LPC_STATUS_SMI_PENDING)) - need_smi = 1; - MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SMI_PENDING; - } else { - MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SMI_PENDING; - } - - if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) { - /* Generate SCI for every event */ - need_sci = 1; - MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SCI_PENDING; - } else { - MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SCI_PENDING; - } - - /* Copy host events to mapped memory */ - *(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) = - lpc_get_host_events(); - - task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF); - - /* Process the wake events. */ - lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE)); - - /* Send pulse on SMI signal if needed */ - if (need_smi) - lpc_generate_smi(); - - /* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */ - if (need_sci) - lpc_generate_sci(); -} - -static void lpc_send_response_packet(struct host_packet *pkt) -{ - /* Ignore in-progress on LPC since interface is synchronous anyway */ - if (pkt->driver_result == EC_RES_IN_PROGRESS) - return; - - /* Write result to the data byte. */ - MEC1322_ACPI_EC_EC2OS(1, 0) = pkt->driver_result; - - /* Clear the busy bit, so the host knows the EC is done. */ - MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING; -} - -/* - * Most registers in LPC module are reset when the host is off. We need to - * set up LPC again when the host is starting up. - */ -static void setup_lpc(void) -{ - gpio_config_module(MODULE_LPC, 1); - - /* Set up interrupt on LRESET# deassert */ - MEC1322_INT_SOURCE(19) = BIT(1); - MEC1322_INT_ENABLE(19) |= BIT(1); - MEC1322_INT_BLK_EN |= BIT(19); - task_enable_irq(MEC1322_IRQ_GIRQ19); - - /* Set up ACPI0 for 0x62/0x66 */ - MEC1322_LPC_ACPI_EC0_BAR = 0x00628304; - MEC1322_INT_ENABLE(15) |= BIT(6); - MEC1322_INT_BLK_EN |= BIT(15); - /* Clear STATUS_PROCESSING bit in case it was set during sysjump */ - MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING; - task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF); - - /* Set up ACPI1 for 0x200/0x204 */ - MEC1322_LPC_ACPI_EC1_BAR = 0x02008407; - MEC1322_INT_ENABLE(15) |= BIT(8); - MEC1322_INT_BLK_EN |= BIT(15); - MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING; - task_enable_irq(MEC1322_IRQ_ACPIEC1_IBF); - - /* Set up 8042 interface at 0x60/0x64 */ - MEC1322_LPC_8042_BAR = 0x00608104; - - /* Set up indication of Auxiliary sts */ - MEC1322_8042_KB_CTRL |= BIT(7); - - MEC1322_8042_ACT |= 1; - MEC1322_INT_ENABLE(15) |= (BIT(13) | BIT(14)); - MEC1322_INT_BLK_EN |= BIT(15); - task_enable_irq(MEC1322_IRQ_8042EM_IBF); - task_enable_irq(MEC1322_IRQ_8042EM_OBF); - -#ifndef CONFIG_KEYBOARD_IRQ_GPIO - /* Set up SERIRQ for keyboard */ - MEC1322_8042_KB_CTRL |= BIT(5); - MEC1322_LPC_SIRQ(1) = 0x01; -#endif - - /* Set up EMI module for memory mapped region, base address 0x800 */ - MEC1322_LPC_EMI_BAR = 0x0800800f; - MEC1322_INT_ENABLE(15) |= BIT(2); - MEC1322_INT_BLK_EN |= BIT(15); - task_enable_irq(MEC1322_IRQ_EMI); - - /* Access data RAM through alias address */ - MEC1322_EMI_MBA0 = (uint32_t)mem_mapped - 0x118000 + 0x20000000; - - /* - * Limit EMI read / write range. First 256 bytes are RW for host - * commands. Second 256 bytes are RO for mem-mapped data. - */ - MEC1322_EMI_MRL0 = 0x200; - MEC1322_EMI_MWL0 = 0x100; - - /* Set up Mailbox for Port80 trapping */ - MEC1322_MBX_INDEX = 0xff; - MEC1322_LPC_MAILBOX_BAR = 0x00808901; - - /* We support LPC args and version 3 protocol */ - *(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) = - EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED | - EC_HOST_CMD_FLAG_VERSION_3; - - /* Sufficiently initialized */ - init_done = 1; - - /* Update host events now that we can copy them to memmap */ - lpc_update_host_event_status(); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, setup_lpc, HOOK_PRIO_FIRST); - -static void lpc_init(void) -{ - /* Activate LPC interface */ - MEC1322_LPC_ACT |= 1; - - /* - * Ring Oscillator not permitted to shut down - * until LPC activate bit is cleared - */ - MEC1322_LPC_CLK_CTRL |= 3; - - /* Initialize host args and memory map to all zero */ - memset(lpc_host_args, 0, sizeof(*lpc_host_args)); - memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE); - - setup_lpc(); -} -/* - * Set prio to higher than default; this way LPC memory mapped data is ready - * before other inits try to initialize their memmap data. - */ -DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC); - -#ifdef CONFIG_CHIPSET_RESET_HOOK -static void lpc_chipset_reset(void) -{ - hook_notify(HOOK_CHIPSET_RESET); -} -DECLARE_DEFERRED(lpc_chipset_reset); -#endif - -static void girq19_interrupt(void) -{ - /* Check interrupt result for LRESET# trigger */ - if (MEC1322_INT_RESULT(19) & BIT(1)) { - /* Initialize LPC module when LRESET# is deasserted */ - if (!lpc_get_pltrst_asserted()) { - setup_lpc(); - } else { - /* Store port 80 reset event */ - port_80_write(PORT_80_EVENT_RESET); - -#ifdef CONFIG_CHIPSET_RESET_HOOK - /* Notify HOOK_CHIPSET_RESET */ - hook_call_deferred(&lpc_chipset_reset_data, MSEC); -#endif - } - - CPRINTS("LPC RESET# %sasserted", - lpc_get_pltrst_asserted() ? "" : "de"); - - /* Clear interrupt source */ - MEC1322_INT_SOURCE(19) = BIT(1); - } -} -DECLARE_IRQ(MEC1322_IRQ_GIRQ19, girq19_interrupt, 1); - -static void emi_interrupt(void) -{ - port_80_write(MEC1322_EMI_H2E_MBX); -} -DECLARE_IRQ(MEC1322_IRQ_EMI, emi_interrupt, 1); - -/* - * Port80 POST code polling limitation: - * - POST code 0xFF is ignored. - */ -int port_80_read(void) -{ - int data; - - /* read MBX_INDEX for POST code */ - data = MEC1322_MBX_INDEX; - - /* clear MBX_INDEX for next POST code*/ - MEC1322_MBX_INDEX = 0xff; - - /* mark POST code 0xff as invalid */ - if (data == 0xff) - data = PORT_80_IGNORE; - - return data; -} - -static void acpi_0_interrupt(void) -{ - uint8_t value, result, is_cmd; - - is_cmd = MEC1322_ACPI_EC_STATUS(0) & EC_LPC_STATUS_LAST_CMD; - - /* Set the bust bi */ - MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_PROCESSING; - - /* Read command/data; this clears the FRMH bit. */ - value = MEC1322_ACPI_EC_OS2EC(0, 0); - - /* Handle whatever this was. */ - if (acpi_ap_to_ec(is_cmd, value, &result)) - MEC1322_ACPI_EC_EC2OS(0, 0) = result; - - /* Clear the busy bit */ - MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING; - - /* - * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer - * Full condition on the kernel channel. - */ - lpc_generate_sci(); -} -DECLARE_IRQ(MEC1322_IRQ_ACPIEC0_IBF, acpi_0_interrupt, 1); - -void acpi_1_interrupt(void) -{ - uint8_t st = MEC1322_ACPI_EC_STATUS(1); - if (!(st & EC_LPC_STATUS_FROM_HOST) || !(st & EC_LPC_STATUS_LAST_CMD)) - return; - - /* Set the busy bit */ - MEC1322_ACPI_EC_STATUS(1) |= EC_LPC_STATUS_PROCESSING; - - /* - * Read the command byte. This clears the FRMH bit in - * the status byte. - */ - host_cmd_args.command = MEC1322_ACPI_EC_OS2EC(1, 0); - - host_cmd_args.result = EC_RES_SUCCESS; - host_cmd_flags = lpc_host_args->flags; - - /* We only support new style command (v3) now */ - if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) { - lpc_packet.send_response = lpc_send_response_packet; - - lpc_packet.request = (const void *)lpc_get_hostcmd_data_range(); - lpc_packet.request_temp = params_copy; - lpc_packet.request_max = sizeof(params_copy); - /* Don't know the request size so pass in the entire buffer */ - lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE; - - lpc_packet.response = (void *)lpc_get_hostcmd_data_range(); - lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE; - lpc_packet.response_size = 0; - - lpc_packet.driver_result = EC_RES_SUCCESS; - host_packet_receive(&lpc_packet); - return; - } else { - /* Old style command unsupported */ - host_cmd_args.result = EC_RES_INVALID_COMMAND; - } - - /* Hand off to host command handler */ - host_command_received(&host_cmd_args); -} -DECLARE_IRQ(MEC1322_IRQ_ACPIEC1_IBF, acpi_1_interrupt, 1); - -#ifdef HAS_TASK_KEYPROTO -void kb_ibf_interrupt(void) -{ - if (lpc_keyboard_input_pending()) - keyboard_host_write(MEC1322_8042_H2E, - MEC1322_8042_STS & BIT(3)); - task_wake(TASK_ID_KEYPROTO); -} -DECLARE_IRQ(MEC1322_IRQ_8042EM_IBF, kb_ibf_interrupt, 1); - -void kb_obf_interrupt(void) -{ - task_wake(TASK_ID_KEYPROTO); -} -DECLARE_IRQ(MEC1322_IRQ_8042EM_OBF, kb_obf_interrupt, 1); -#endif - -int lpc_keyboard_has_char(void) -{ - return (MEC1322_8042_STS & BIT(0)) ? 1 : 0; -} - -int lpc_keyboard_input_pending(void) -{ - return (MEC1322_8042_STS & BIT(1)) ? 1 : 0; -} - -void lpc_keyboard_put_char(uint8_t chr, int send_irq) -{ - MEC1322_8042_E2H = chr; - if (send_irq) - keyboard_irq_assert(); -} - -void lpc_keyboard_clear_buffer(void) -{ - volatile char unused __attribute__((unused)); - - unused = MEC1322_8042_OBF_CLR; -} - -void lpc_keyboard_resume_irq(void) -{ - if (lpc_keyboard_has_char()) - keyboard_irq_assert(); -} - -void lpc_set_acpi_status_mask(uint8_t mask) -{ - MEC1322_ACPI_EC_STATUS(0) |= mask; -} - -void lpc_clear_acpi_status_mask(uint8_t mask) -{ - MEC1322_ACPI_EC_STATUS(0) &= ~mask; -} - -int lpc_get_pltrst_asserted(void) -{ - return (MEC1322_LPC_BUS_MONITOR & (1 << 1)) ? 1 : 0; -} - -/* Enable LPC ACPI-EC0 interrupts */ -void lpc_enable_acpi_interrupts(void) -{ - task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF); -} - -/* Disable LPC ACPI-EC0 interrupts */ -void lpc_disable_acpi_interrupts(void) -{ - task_disable_irq(MEC1322_IRQ_ACPIEC0_IBF); -} - -/* On boards without a host, this command is used to set up LPC */ -static int lpc_command_init(int argc, char **argv) -{ - lpc_init(); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(lpcinit, lpc_command_init, NULL, NULL); - -/* Get protocol information */ -static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args) -{ - struct ec_response_get_protocol_info *r = args->response; - - memset(r, 0, sizeof(*r)); - r->protocol_versions = BIT(3); - r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; - r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; - r->flags = 0; - - args->response_size = sizeof(*r); - - return EC_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info, - EC_VER_MASK(0)); diff --git a/chip/mec1322/port80.c b/chip/mec1322/port80.c deleted file mode 100644 index cbc87d8a88..0000000000 --- a/chip/mec1322/port80.c +++ /dev/null @@ -1,103 +0,0 @@ -/* Copyright 2015 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Port 80 Timer Interrupt for MEC1322 */ - -#include "common.h" -#include "console.h" -#include "hooks.h" -#include "lpc.h" -#include "port80.h" -#include "registers.h" -#include "task.h" - -/* Fire timer interrupt every 1000 usec to check for port80 data. */ -#define POLL_PERIOD_USEC 1000 -/* After 30 seconds of no port 80 data, disable the timer interrupt. */ -#define INTERRUPT_DISABLE_TIMEOUT_SEC 30 -#define INTERRUPT_DISABLE_IDLE_COUNT \ - (INTERRUPT_DISABLE_TIMEOUT_SEC * 1000000 / POLL_PERIOD_USEC) - -/* Count the number of consecutive interrupts with no port 80 data. */ -static int idle_count; - -static void port_80_interrupt_enable(void) -{ - idle_count = 0; - - /* Enable the interrupt. */ - task_enable_irq(MEC1322_IRQ_TIMER16_1); - /* Enable and start the timer. */ - MEC1322_TMR16_CTL(1) |= 1 | BIT(5); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, port_80_interrupt_enable, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_RESET, port_80_interrupt_enable, HOOK_PRIO_DEFAULT); - -static void port_80_interrupt_disable(void) -{ - /* Disable the timer block. */ - MEC1322_TMR16_CTL(1) &= ~1; - /* Disable the interrupt. */ - task_disable_irq(MEC1322_IRQ_TIMER16_1); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, port_80_interrupt_disable, - HOOK_PRIO_DEFAULT); - -/* - * The port 80 interrupt will use TIMER16 instance 1 for a 1ms countdown - * timer. This timer is on GIRQ23, bit 1. - */ -static void port_80_interrupt_init(void) -{ - uint32_t val = 0; - - /* - * The timers are driven by a 48MHz oscillator. Prescale down to - * 1MHz. 48MHz/48 -> 1MHz - */ - val = MEC1322_TMR16_CTL(1); - val = (val & 0xFFFF) | (47 << 16); - /* Automatically restart the timer. */ - val |= BIT(3); - /* The counter should decrement. */ - val &= ~BIT(2); - MEC1322_TMR16_CTL(1) = val; - - /* Set the reload value(us). */ - MEC1322_TMR16_PRE(1) = POLL_PERIOD_USEC; - - /* Clear the status if any. */ - MEC1322_TMR16_STS(1) |= 1; - - /* Clear any pending interrupt. */ - MEC1322_INT_SOURCE(23) = BIT(1); - /* Enable IRQ vector 23. */ - MEC1322_INT_BLK_EN |= BIT(23); - /* Enable the interrupt. */ - MEC1322_TMR16_IEN(1) |= 1; - MEC1322_INT_ENABLE(23) = BIT(1); - - port_80_interrupt_enable(); -} -DECLARE_HOOK(HOOK_INIT, port_80_interrupt_init, HOOK_PRIO_DEFAULT); - -static void port_80_interrupt(void) -{ - int data; - - MEC1322_TMR16_STS(1) = 1; /* Ack the interrupt */ - if (BIT(1) & MEC1322_INT_RESULT(23)) { - data = port_80_read(); - - if (data != PORT_80_IGNORE) { - idle_count = 0; - port_80_write(data); - } - } - - if (++idle_count >= INTERRUPT_DISABLE_IDLE_COUNT) - port_80_interrupt_disable(); -} -DECLARE_IRQ(MEC1322_IRQ_TIMER16_1, port_80_interrupt, 2); diff --git a/chip/mec1322/pwm.c b/chip/mec1322/pwm.c deleted file mode 100644 index bcb9360638..0000000000 --- a/chip/mec1322/pwm.c +++ /dev/null @@ -1,84 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* PWM control module for MEC1322 */ - -#include "hooks.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "util.h" - -/* - * PWMs that must remain active in low-power idle - MEC1322_PCR_EC_SLP_EN - * bit mask. - */ -static uint32_t pwm_keep_awake_mask; - -void pwm_enable(enum pwm_channel ch, int enabled) -{ - int id = pwm_channels[ch].channel; - - if (enabled) { - MEC1322_PWM_CFG(id) |= 0x1; - if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP) - pwm_keep_awake_mask |= MEC1322_PCR_EC_SLP_EN_PWM(id); - } else { - MEC1322_PWM_CFG(id) &= ~0x1; - pwm_keep_awake_mask &= ~MEC1322_PCR_EC_SLP_EN_PWM(id); - } -} - -int pwm_get_enabled(enum pwm_channel ch) -{ - return MEC1322_PWM_CFG(pwm_channels[ch].channel) & 0x1; -} - -void pwm_set_duty(enum pwm_channel ch, int percent) -{ - int id = pwm_channels[ch].channel; - - if (percent < 0) - percent = 0; - else if (percent > 100) - percent = 100; - - MEC1322_PWM_ON(id) = percent; - MEC1322_PWM_OFF(id) = 100 - percent; -} - -int pwm_get_duty(enum pwm_channel ch) -{ - return MEC1322_PWM_ON(pwm_channels[ch].channel); -} - -uint32_t pwm_get_keep_awake_mask(void) -{ - return pwm_keep_awake_mask; -} - -static void pwm_configure(int ch, int active_low, int clock_low) -{ - /* - * clock_low=0 selects the 48MHz Ring Oscillator source - * clock_low=1 selects the 100kHz_Clk source - */ - MEC1322_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */ - (active_low ? BIT(2) : 0) | - (clock_low ? BIT(1) : 0); -} - -static void pwm_init(void) -{ - int i; - - for (i = 0; i < PWM_CH_COUNT; ++i) { - pwm_configure(pwm_channels[i].channel, - pwm_channels[i].flags & PWM_CONFIG_ACTIVE_LOW, - pwm_channels[i].flags & PWM_CONFIG_ALT_CLOCK); - pwm_set_duty(i, 0); - } -} -DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM); diff --git a/chip/mec1322/pwm_chip.h b/chip/mec1322/pwm_chip.h deleted file mode 100644 index 69d8de094a..0000000000 --- a/chip/mec1322/pwm_chip.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MEC1322-specific PWM module for Chrome EC */ -#ifndef __CROS_EC_PWM_CHIP_H -#define __CROS_EC_PWM_CHIP_H - -/* Data structure to define PWM channels. */ -struct pwm_t { - /* PWM Channel ID */ - int channel; - - /* PWM channel flags. See include/pwm.h */ - uint32_t flags; -}; - -extern const struct pwm_t pwm_channels[]; - -/* - * Returns PWMs that must remain active in low-power idle - - * MEC1322_PCR_EC_SLP_EN bit mask. - */ -uint32_t pwm_get_keep_awake_mask(void); -#endif /* __CROS_EC_PWM_CHIP_H */ diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h deleted file mode 100644 index 1a758003c9..0000000000 --- a/chip/mec1322/registers.h +++ /dev/null @@ -1,493 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for MEC1322 processor - */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -#include "common.h" - -/* Helper function for RAM address aliasing */ -#define MEC1322_RAM_ALIAS(x) ((x) >= 0x118000 ? (x)-0x118000 + 0x20000000 : (x)) - -/* EC Chip Configuration */ -#define MEC1322_CHIP_BASE 0x400fff00 -#define MEC1322_CHIP_DEV_ID REG8(MEC1322_CHIP_BASE + 0x20) -#define MEC1322_CHIP_DEV_REV REG8(MEC1322_CHIP_BASE + 0x21) - -/* Power/Clocks/Resets */ -#define MEC1322_PCR_BASE 0x40080100 -#define MEC1322_PCR_CHIP_SLP_EN REG32(MEC1322_PCR_BASE + 0x0) -#define MEC1322_PCR_CHIP_CLK_REQ REG32(MEC1322_PCR_BASE + 0x4) -#define MEC1322_PCR_EC_SLP_EN REG32(MEC1322_PCR_BASE + 0x8) -/* Command all blocks to sleep */ -#define MEC1322_PCR_EC_SLP_EN_SLEEP 0xe0700ff7 -#define MEC1322_PCR_EC_SLP_EN_PWM(n) (1 << ((n) ? (19 + (n)) : 4)) -#define MEC1322_PCR_EC_SLP_EN_PWM3 BIT(22) -#define MEC1322_PCR_EC_SLP_EN_PWM2 BIT(21) -#define MEC1322_PCR_EC_SLP_EN_PWM1 BIT(20) -#define MEC1322_PCR_EC_SLP_EN_PWM0 BIT(4) -/* Allow all blocks to request clocks */ -#define MEC1322_PCR_EC_SLP_EN_WAKE (~0xe0700ff7) -#define MEC1322_PCR_EC_CLK_REQ REG32(MEC1322_PCR_BASE + 0xc) -#define MEC1322_PCR_HOST_SLP_EN REG32(MEC1322_PCR_BASE + 0x10) -/* Command all blocks to sleep */ -#define MEC1322_PCR_HOST_SLP_EN_SLEEP 0x5f003 -/* Allow all blocks to request clocks */ -#define MEC1322_PCR_HOST_SLP_EN_WAKE (~0x5f003) -#define MEC1322_PCR_HOST_CLK_REQ REG32(MEC1322_PCR_BASE + 0x14) -#define MEC1322_PCR_SYS_SLP_CTL REG32(MEC1322_PCR_BASE + 0x18) -#define MEC1322_PCR_PROC_CLK_CTL REG32(MEC1322_PCR_BASE + 0x20) -#define MEC1322_PCR_EC_SLP_EN2 REG32(MEC1322_PCR_BASE + 0x24) -/* Mask to command all blocks to sleep */ -#define MEC1322_PCR_EC_SLP_EN2_SLEEP 0x1ffffff8 -/* Allow all blocks to request clocks */ -#define MEC1322_PCR_EC_SLP_EN2_WAKE (~0x03fffff8) -#define MEC1322_PCR_EC_CLK_REQ2 REG32(MEC1322_PCR_BASE + 0x28) -#define MEC1322_PCR_SLOW_CLK_CTL REG32(MEC1322_PCR_BASE + 0x2c) -#define MEC1322_PCR_CHIP_OSC_ID REG32(MEC1322_PCR_BASE + 0x30) -#define MEC1322_PCR_CHIP_PWR_RST REG32(MEC1322_PCR_BASE + 0x34) -#define MEC1322_PCR_CHIP_RST_EN REG32(MEC1322_PCR_BASE + 0x38) -#define MEC1322_PCR_HOST_RST_EN REG32(MEC1322_PCR_BASE + 0x3c) -#define MEC1322_PCR_EC_RST_EN REG32(MEC1322_PCR_BASE + 0x40) -#define MEC1322_PCR_EC_RST_EN2 REG32(MEC1322_PCR_BASE + 0x44) -#define MEC1322_PCR_PWR_RST_CTL REG32(MEC1322_PCR_BASE + 0x48) - -/* Bit defines for MEC1322_PCR_CHIP_PWR_RST */ -#define MEC1322_PWR_RST_STS_VCC1 BIT(6) -#define MEC1322_PWR_RST_STS_VBAT BIT(5) - -/* EC Subsystem */ -#define MEC1322_EC_BASE 0x4000fc00 -#define MEC1322_EC_INT_CTRL REG32(MEC1322_EC_BASE + 0x18) -#define MEC1322_EC_TRACE_EN REG32(MEC1322_EC_BASE + 0x1c) -#define MEC1322_EC_JTAG_EN REG32(MEC1322_EC_BASE + 0x20) -#define MEC1322_EC_WDT_CNT REG32(MEC1322_EC_BASE + 0x28) -#define MEC1322_EC_ADC_VREF_PD REG32(MEC1322_EC_BASE + 0x38) - -/* Interrupt aggregator */ -#define MEC1322_INT_BASE 0x4000c000 -#define MEC1322_INTx_BASE(x) (MEC1322_INT_BASE + ((x)-8) * 0x14) -#define MEC1322_INT_SOURCE(x) REG32(MEC1322_INTx_BASE(x) + 0x0) -#define MEC1322_INT_ENABLE(x) REG32(MEC1322_INTx_BASE(x) + 0x4) -#define MEC1322_INT_RESULT(x) REG32(MEC1322_INTx_BASE(x) + 0x8) -#define MEC1322_INT_DISABLE(x) REG32(MEC1322_INTx_BASE(x) + 0xc) -#define MEC1322_INT_BLK_EN REG32(MEC1322_INT_BASE + 0x200) -#define MEC1322_INT_BLK_DIS REG32(MEC1322_INT_BASE + 0x204) -#define MEC1322_INT_BLK_IRQ REG32(MEC1322_INT_BASE + 0x208) - -/* UART */ -#define MEC1322_UART_CONFIG_BASE 0x400f1f00 -#define MEC1322_UART_RUNTIME_BASE 0x400f1c00 - -#define MEC1322_UART_ACT REG8(MEC1322_UART_CONFIG_BASE + 0x30) -#define MEC1322_UART_CFG REG8(MEC1322_UART_CONFIG_BASE + 0xf0) - -/* DLAB=0 */ -#define MEC1322_UART_RB /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x0) -#define MEC1322_UART_TB /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x0) -#define MEC1322_UART_IER REG8(MEC1322_UART_RUNTIME_BASE + 0x1) -/* DLAB=1 */ -#define MEC1322_UART_PBRG0 REG8(MEC1322_UART_RUNTIME_BASE + 0x0) -#define MEC1322_UART_PBRG1 REG8(MEC1322_UART_RUNTIME_BASE + 0x1) - -#define MEC1322_UART_FCR /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2) -#define MEC1322_UART_IIR /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2) -#define MEC1322_UART_LCR REG8(MEC1322_UART_RUNTIME_BASE + 0x3) -#define MEC1322_UART_MCR REG8(MEC1322_UART_RUNTIME_BASE + 0x4) -#define MEC1322_UART_LSR REG8(MEC1322_UART_RUNTIME_BASE + 0x5) -#define MEC1322_UART_MSR REG8(MEC1322_UART_RUNTIME_BASE + 0x6) -#define MEC1322_UART_SCR REG8(MEC1322_UART_RUNTIME_BASE + 0x7) - -/* Bit defines for MEC1322_UART_LSR */ -#define MEC1322_LSR_TX_EMPTY BIT(5) - -/* GPIO */ -#define MEC1322_GPIO_BASE 0x40081000 - -static inline uintptr_t gpio_port_base(int port_id) -{ - int oct = (port_id / 10) * 8 + port_id % 10; - return MEC1322_GPIO_BASE + oct * 0x20; -} -#define MEC1322_GPIO_CTL(port, id) REG32(gpio_port_base(port) + (id << 2)) - -#define UNIMPLEMENTED_GPIO_BANK 0 - -/* Timer */ -#define MEC1322_TMR16_BASE(x) (0x40000c00 + (x)*0x20) -#define MEC1322_TMR32_BASE(x) (0x40000c80 + (x)*0x20) - -#define MEC1322_TMR16_CNT(x) REG32(MEC1322_TMR16_BASE(x) + 0x0) -#define MEC1322_TMR16_PRE(x) REG32(MEC1322_TMR16_BASE(x) + 0x4) -#define MEC1322_TMR16_STS(x) REG32(MEC1322_TMR16_BASE(x) + 0x8) -#define MEC1322_TMR16_IEN(x) REG32(MEC1322_TMR16_BASE(x) + 0xc) -#define MEC1322_TMR16_CTL(x) REG32(MEC1322_TMR16_BASE(x) + 0x10) -#define MEC1322_TMR32_CNT(x) REG32(MEC1322_TMR32_BASE(x) + 0x0) -#define MEC1322_TMR32_PRE(x) REG32(MEC1322_TMR32_BASE(x) + 0x4) -#define MEC1322_TMR32_STS(x) REG32(MEC1322_TMR32_BASE(x) + 0x8) -#define MEC1322_TMR32_IEN(x) REG32(MEC1322_TMR32_BASE(x) + 0xc) -#define MEC1322_TMR32_CTL(x) REG32(MEC1322_TMR32_BASE(x) + 0x10) - -/* Watchdog */ -#define MEC1322_WDG_BASE 0x40000400 -#define MEC1322_WDG_LOAD REG16(MEC1322_WDG_BASE + 0x0) -#define MEC1322_WDG_CTL REG8(MEC1322_WDG_BASE + 0x4) -#define MEC1322_WDG_KICK REG8(MEC1322_WDG_BASE + 0x8) -#define MEC1322_WDG_CNT REG16(MEC1322_WDG_BASE + 0xc) - -/* VBAT */ -#define MEC1322_VBAT_BASE 0x4000a400 -#define MEC1322_VBAT_STS REG32(MEC1322_VBAT_BASE + 0x0) -#define MEC1322_VBAT_CE REG32(MEC1322_VBAT_BASE + 0x8) -#define MEC1322_VBAT_RAM(x) REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x)) - -/* Bit definition for MEC1322_VBAT_STS */ -#define MEC1322_VBAT_STS_WDT BIT(5) - -/* Miscellaneous firmware control fields - * scratch pad index cannot be more than 16 as - * mec has 64 bytes = 16 indexes of scratchpad RAM - */ -#define MEC1322_IMAGETYPE_IDX 15 - -/* LPC */ -#define MEC1322_LPC_CFG_BASE 0x400f3300 -#define MEC1322_LPC_ACT REG8(MEC1322_LPC_CFG_BASE + 0x30) -#define MEC1322_LPC_SIRQ(x) REG8(MEC1322_LPC_CFG_BASE + 0x40 + (x)) -#define MEC1322_LPC_CFG_BAR REG32(MEC1322_LPC_CFG_BASE + 0x60) -#define MEC1322_LPC_EMI_BAR REG32(MEC1322_LPC_CFG_BASE + 0x64) -#define MEC1322_LPC_UART_BAR REG32(MEC1322_LPC_CFG_BASE + 0x68) -#define MEC1322_LPC_8042_BAR REG32(MEC1322_LPC_CFG_BASE + 0x78) -#define MEC1322_LPC_ACPI_EC0_BAR REG32(MEC1322_LPC_CFG_BASE + 0x88) -#define MEC1322_LPC_ACPI_EC1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x8c) -#define MEC1322_LPC_ACPI_PM1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x90) -#define MEC1322_LPC_PORT92_BAR REG32(MEC1322_LPC_CFG_BASE + 0x94) -#define MEC1322_LPC_MAILBOX_BAR REG32(MEC1322_LPC_CFG_BASE + 0x98) -#define MEC1322_LPC_RTC_BAR REG32(MEC1322_LPC_CFG_BASE + 0x9c) -#define MEC1322_LPC_MEM_BAR REG32(MEC1322_LPC_CFG_BASE + 0xa0) -#define MEC1322_LPC_MEM_BAR_CFG REG32(MEC1322_LPC_CFG_BASE + 0xa4) - -#define MEC1322_LPC_RT_BASE 0x400f3100 -#define MEC1322_LPC_BUS_MONITOR REG32(MEC1322_LPC_RT_BASE + 0x4) -#define MEC1322_LPC_CLK_CTRL REG32(MEC1322_LPC_RT_BASE + 0x10) -#define MEC1322_LPC_MEM_HOST_CFG REG32(MEC1322_LPC_RT_BASE + 0xfc) - -/* EMI */ -#define MEC1322_EMI_BASE 0x400f0100 -#define MEC1322_EMI_H2E_MBX REG8(MEC1322_EMI_BASE + 0x0) -#define MEC1322_EMI_E2H_MBX REG8(MEC1322_EMI_BASE + 0x1) -#define MEC1322_EMI_MBA0 REG32(MEC1322_EMI_BASE + 0x4) -#define MEC1322_EMI_MRL0 REG16(MEC1322_EMI_BASE + 0x8) -#define MEC1322_EMI_MWL0 REG16(MEC1322_EMI_BASE + 0xa) -#define MEC1322_EMI_MBA1 REG32(MEC1322_EMI_BASE + 0xc) -#define MEC1322_EMI_MRL1 REG16(MEC1322_EMI_BASE + 0x10) -#define MEC1322_EMI_MWL1 REG16(MEC1322_EMI_BASE + 0x12) -#define MEC1322_EMI_ISR REG16(MEC1322_EMI_BASE + 0x14) -#define MEC1322_EMI_HCE REG16(MEC1322_EMI_BASE + 0x16) - -#define MEC1322_EMI_RT_BASE 0x400f0000 -#define MEC1322_EMI_ISR_B0 REG8(MEC1322_EMI_RT_BASE + 0x8) -#define MEC1322_EMI_ISR_B1 REG8(MEC1322_EMI_RT_BASE + 0x9) -#define MEC1322_EMI_IMR_B0 REG8(MEC1322_EMI_RT_BASE + 0xa) -#define MEC1322_EMI_IMR_B1 REG8(MEC1322_EMI_RT_BASE + 0xb) - -/* Mailbox */ -#define MEC1322_MBX_RT_BASE 0x400f2400 -#define MEC1322_MBX_INDEX REG8(MEC1322_MBX_RT_BASE + 0x0) -#define MEC1322_MBX_DATA REG8(MEC1322_MBX_RT_BASE + 0x1) - -#define MEC1322_MBX_BASE 0x400f2500 -#define MEC1322_MBX_H2E_MBX REG8(MEC1322_MBX_BASE + 0x0) -#define MEC1322_MBX_E2H_MBX REG8(MEC1322_MBX_BASE + 0x4) -#define MEC1322_MBX_ISR REG8(MEC1322_MBX_BASE + 0x8) -#define MEC1322_MBX_IMR REG8(MEC1322_MBX_BASE + 0xc) -#define MEC1322_MBX_REG(x) REG8(MEC1322_MBX_BASE + 0x10 + (x)) - -/* PWM */ -#define MEC1322_PWM_BASE(x) (0x40005800 + (x)*0x10) -#define MEC1322_PWM_ON(x) REG32(MEC1322_PWM_BASE(x) + 0x00) -#define MEC1322_PWM_OFF(x) REG32(MEC1322_PWM_BASE(x) + 0x04) -#define MEC1322_PWM_CFG(x) REG32(MEC1322_PWM_BASE(x) + 0x08) - -/* ACPI */ -#define MEC1322_ACPI_EC_BASE(x) (0x400f0c00 + (x)*0x400) -#define MEC1322_ACPI_EC_EC2OS(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x100 + (y)) -#define MEC1322_ACPI_EC_STATUS(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x104) -#define MEC1322_ACPI_EC_BYTE_CTL(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x105) -#define MEC1322_ACPI_EC_OS2EC(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x108 + (y)) - -#define MEC1322_ACPI_PM_RT_BASE 0x400f1400 -#define MEC1322_ACPI_PM1_STS1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x0) -#define MEC1322_ACPI_PM1_STS2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x1) -#define MEC1322_ACPI_PM1_EN1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x2) -#define MEC1322_ACPI_PM1_EN2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x3) -#define MEC1322_ACPI_PM1_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x4) -#define MEC1322_ACPI_PM1_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x5) -#define MEC1322_ACPI_PM2_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x6) -#define MEC1322_ACPI_PM2_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x7) -#define MEC1322_ACPI_PM_EC_BASE 0x400f1500 -#define MEC1322_ACPI_PM_STS REG8(MEC1322_ACPI_PM_EC_BASE + 0x10) - -/* 8042 */ -#define MEC1322_8042_BASE 0x400f0400 -#define MEC1322_8042_OBF_CLR REG8(MEC1322_8042_BASE + 0x0) -#define MEC1322_8042_H2E REG8(MEC1322_8042_BASE + 0x100) -#define MEC1322_8042_E2H REG8(MEC1322_8042_BASE + 0x100) -#define MEC1322_8042_STS REG8(MEC1322_8042_BASE + 0x104) -#define MEC1322_8042_KB_CTRL REG8(MEC1322_8042_BASE + 0x108) -#define MEC1322_8042_PCOBF REG8(MEC1322_8042_BASE + 0x114) -#define MEC1322_8042_ACT REG8(MEC1322_8042_BASE + 0x330) - -/* FAN */ -#define MEC1322_FAN_BASE 0x4000a000 -#define MEC1322_FAN_SETTING REG8(MEC1322_FAN_BASE + 0x0) -#define MEC1322_FAN_PWM_DIVIDE REG8(MEC1322_FAN_BASE + 0x1) -#define MEC1322_FAN_CFG1 REG8(MEC1322_FAN_BASE + 0x2) -#define MEC1322_FAN_CFG2 REG8(MEC1322_FAN_BASE + 0x3) -#define MEC1322_FAN_GAIN REG8(MEC1322_FAN_BASE + 0x5) -#define MEC1322_FAN_SPIN_UP REG8(MEC1322_FAN_BASE + 0x6) -#define MEC1322_FAN_STEP REG8(MEC1322_FAN_BASE + 0x7) -#define MEC1322_FAN_MIN_DRV REG8(MEC1322_FAN_BASE + 0x8) -#define MEC1322_FAN_VALID_CNT REG8(MEC1322_FAN_BASE + 0x9) -#define MEC1322_FAN_DRV_FAIL REG16(MEC1322_FAN_BASE + 0xa) -#define MEC1322_FAN_TARGET REG16(MEC1322_FAN_BASE + 0xc) -#define MEC1322_FAN_READING REG16(MEC1322_FAN_BASE + 0xe) -#define MEC1322_FAN_BASE_FREQ REG8(MEC1322_FAN_BASE + 0x10) -#define MEC1322_FAN_STATUS REG8(MEC1322_FAN_BASE + 0x11) - -/* I2C */ -#define MEC1322_I2C0_BASE 0x40001800 -#define MEC1322_I2C1_BASE 0x4000ac00 -#define MEC1322_I2C2_BASE 0x4000b000 -#define MEC1322_I2C3_BASE 0x4000b400 -#define MEC1322_I2C_BASESEP 0x00000400 -#define MEC1322_I2C_ADDR(controller, offset) \ - (offset + \ - (controller == 0 ? \ - MEC1322_I2C0_BASE : \ - MEC1322_I2C1_BASE + MEC1322_I2C_BASESEP * (controller - 1))) - -/* - * MEC1322 has five ports distributed among four controllers. Locking must - * occur by-controller (not by-port). - */ -enum mec1322_i2c_port { - MEC1322_I2C0_0 = 0, /* Controller 0, port 0 */ - MEC1322_I2C0_1 = 1, /* Controller 0, port 1 */ - MEC1322_I2C1 = 2, /* Controller 1 */ - MEC1322_I2C2 = 3, /* Controller 2 */ - MEC1322_I2C3 = 4, /* Controller 3 */ - MEC1322_I2C_PORT_COUNT, -}; - -#define MEC1322_I2C_CTRL(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x0)) -#define MEC1322_I2C_STATUS(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x0)) -#define MEC1322_I2C_OWN_ADDR(ctrl) REG16(MEC1322_I2C_ADDR(ctrl, 0x4)) -#define MEC1322_I2C_DATA(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x8)) -#define MEC1322_I2C_MASTER_CMD(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0xc)) -#define MEC1322_I2C_SLAVE_CMD(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x10)) -#define MEC1322_I2C_PEC(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x14)) -#define MEC1322_I2C_DATA_TIM_2(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x18)) -#define MEC1322_I2C_COMPLETE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x20)) -#define MEC1322_I2C_IDLE_SCALE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x24)) -#define MEC1322_I2C_CONFIG(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x28)) -#define MEC1322_I2C_BUS_CLK(ctrl) REG16(MEC1322_I2C_ADDR(ctrl, 0x2c)) -#define MEC1322_I2C_BLK_ID(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x30)) -#define MEC1322_I2C_REV(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x34)) -#define MEC1322_I2C_BB_CTRL(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x38)) -#define MEC1322_I2C_DATA_TIM(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x40)) -#define MEC1322_I2C_TOUT_SCALE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x44)) -#define MEC1322_I2C_SLAVE_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x48)) -#define MEC1322_I2C_SLAVE_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x4c)) -#define MEC1322_I2C_MASTER_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x50)) -#define MEC1322_I2C_MASTER_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x54)) - -/* Keyboard scan matrix */ -#define MEC1322_KS_BASE 0x40009c00 -#define MEC1322_KS_KSO_SEL REG32(MEC1322_KS_BASE + 0x4) -#define MEC1322_KS_KSI_INPUT REG32(MEC1322_KS_BASE + 0x8) -#define MEC1322_KS_KSI_STATUS REG32(MEC1322_KS_BASE + 0xc) -#define MEC1322_KS_KSI_INT_EN REG32(MEC1322_KS_BASE + 0x10) -#define MEC1322_KS_EXT_CTRL REG32(MEC1322_KS_BASE + 0x14) - -/* ADC */ -#define MEC1322_ADC_BASE 0x40007c00 -#define MEC1322_ADC_CTRL REG32(MEC1322_ADC_BASE + 0x0) -#define MEC1322_ADC_DELAY REG32(MEC1322_ADC_BASE + 0x4) -#define MEC1322_ADC_STS REG32(MEC1322_ADC_BASE + 0x8) -#define MEC1322_ADC_SINGLE REG32(MEC1322_ADC_BASE + 0xc) -#define MEC1322_ADC_REPEAT REG32(MEC1322_ADC_BASE + 0x10) -#define MEC1322_ADC_READ(x) REG32(MEC1322_ADC_BASE + 0x14 + (x)*0x4) - -/* Hibernation timer */ -#define MEC1322_HTIMER_BASE 0x40009800 -#define MEC1322_HTIMER_PRELOAD REG16(MEC1322_HTIMER_BASE + 0x0) -#define MEC1322_HTIMER_CONTROL REG16(MEC1322_HTIMER_BASE + 0x4) -#define MEC1322_HTIMER_COUNT REG16(MEC1322_HTIMER_BASE + 0x8) - -/* SPI */ -#define MEC1322_SPI_BASE(port) (0x40009400 + 0x80 * (port)) -#define MEC1322_SPI_AR(port) REG8(MEC1322_SPI_BASE(port) + 0x00) -#define MEC1322_SPI_CR(port) REG8(MEC1322_SPI_BASE(port) + 0x04) -#define MEC1322_SPI_SR(port) REG8(MEC1322_SPI_BASE(port) + 0x08) -#define MEC1322_SPI_TD(port) REG8(MEC1322_SPI_BASE(port) + 0x0c) -#define MEC1322_SPI_RD(port) REG8(MEC1322_SPI_BASE(port) + 0x10) -#define MEC1322_SPI_CC(port) REG8(MEC1322_SPI_BASE(port) + 0x14) -#define MEC1322_SPI_CG(port) REG8(MEC1322_SPI_BASE(port) + 0x18) - -/* DMA */ -#define MEC1322_DMA_BASE 0x40002400 - -/* - * Available DMA channels. - * - * On MEC1322, any DMA channel may serve any device. Since we have - * 12 channels and 12 devices, we make each channel dedicated to the - * device of the same number. - */ -enum dma_channel { - /* Channel numbers */ - MEC1322_DMAC_I2C0_SLAVE = 0, - MEC1322_DMAC_I2C0_MASTER = 1, - MEC1322_DMAC_I2C1_SLAVE = 2, - MEC1322_DMAC_I2C1_MASTER = 3, - MEC1322_DMAC_I2C2_SLAVE = 4, - MEC1322_DMAC_I2C2_MASTER = 5, - MEC1322_DMAC_I2C3_SLAVE = 6, - MEC1322_DMAC_I2C3_MASTER = 7, - MEC1322_DMAC_SPI0_TX = 8, - MEC1322_DMAC_SPI0_RX = 9, - MEC1322_DMAC_SPI1_TX = 10, - MEC1322_DMAC_SPI1_RX = 11, - - /* Channel count */ - MEC1322_DMAC_COUNT = 12, -}; - -/* Registers for a single channel of the DMA controller */ -struct mec1322_dma_chan { - uint32_t act; /* Activate */ - uint32_t mem_start; /* Memory start address */ - uint32_t mem_end; /* Memory end address */ - uint32_t dev; /* Device address */ - uint32_t ctrl; /* Control */ - uint32_t int_status; /* Interrupt status */ - uint32_t int_enabled; /* Interrupt enabled */ - uint32_t pad; -}; - -/* Always use mec1322_dma_chan_t so volatile keyword is included! */ -typedef volatile struct mec1322_dma_chan mec1322_dma_chan_t; - -/* Common code and header file must use this */ -typedef mec1322_dma_chan_t dma_chan_t; - -/* Registers for the DMA controller */ -struct mec1322_dma_regs { - uint32_t ctrl; - uint32_t data; - uint32_t pad[2]; - mec1322_dma_chan_t chan[MEC1322_DMAC_COUNT]; -}; - -/* Always use mec1322_dma_regs_t so volatile keyword is included! */ -typedef volatile struct mec1322_dma_regs mec1322_dma_regs_t; - -#define MEC1322_DMA_REGS ((mec1322_dma_regs_t *)MEC1322_DMA_BASE) - -/* Bits for DMA channel regs */ -#define MEC1322_DMA_ACT_EN BIT(0) -#define MEC1322_DMA_XFER_SIZE(x) ((x) << 20) -#define MEC1322_DMA_INC_DEV BIT(17) -#define MEC1322_DMA_INC_MEM BIT(16) -#define MEC1322_DMA_DEV(x) ((x) << 9) -#define MEC1322_DMA_TO_DEV BIT(8) -#define MEC1322_DMA_DONE BIT(2) -#define MEC1322_DMA_RUN BIT(0) - -/* IRQ Numbers */ -#define MEC1322_IRQ_I2C_0 0 -#define MEC1322_IRQ_I2C_1 1 -#define MEC1322_IRQ_I2C_2 2 -#define MEC1322_IRQ_I2C_3 3 -#define MEC1322_IRQ_DMA_0 4 -#define MEC1322_IRQ_DMA_1 5 -#define MEC1322_IRQ_DMA_2 6 -#define MEC1322_IRQ_DMA_3 7 -#define MEC1322_IRQ_DMA_4 8 -#define MEC1322_IRQ_DMA_5 9 -#define MEC1322_IRQ_DMA_6 10 -#define MEC1322_IRQ_DMA_7 11 -#define MEC1322_IRQ_LPC 12 -#define MEC1322_IRQ_UART 13 -#define MEC1322_IRQ_EMI 14 -#define MEC1322_IRQ_ACPIEC0_IBF 15 -#define MEC1322_IRQ_ACPIEC0_OBF 16 -#define MEC1322_IRQ_ACPIEC1_IBF 17 -#define MEC1322_IRQ_ACPIEC1_OBF 18 -#define MEC1322_IRQ_ACPIPM1_CTL 19 -#define MEC1322_IRQ_ACPIPM1_EN 20 -#define MEC1322_IRQ_ACPIPM1_STS 21 -#define MEC1322_IRQ_8042EM_OBF 22 -#define MEC1322_IRQ_8042EM_IBF 23 -#define MEC1322_IRQ_MAILBOX 24 -#define MEC1322_IRQ_PECI_HOST 25 -#define MEC1322_IRQ_TACH_0 26 -#define MEC1322_IRQ_TACH_1 27 -#define MEC1322_IRQ_ADC_SNGL 28 -#define MEC1322_IRQ_ADC_RPT 29 -#define MEC1322_IRQ_PS2_0 32 -#define MEC1322_IRQ_PS2_1 33 -#define MEC1322_IRQ_PS2_2 34 -#define MEC1322_IRQ_PS2_3 35 -#define MEC1322_IRQ_SPI0_TX 36 -#define MEC1322_IRQ_SPI0_RX 37 -#define MEC1322_IRQ_HTIMER 38 -#define MEC1322_IRQ_KSC_INT 39 -#define MEC1322_IRQ_MAILBOX_DATA 40 -#define MEC1322_IRQ_TIMER16_0 49 -#define MEC1322_IRQ_TIMER16_1 50 -#define MEC1322_IRQ_TIMER16_2 51 -#define MEC1322_IRQ_TIMER16_3 52 -#define MEC1322_IRQ_TIMER32_0 53 -#define MEC1322_IRQ_TIMER32_1 54 -#define MEC1322_IRQ_SPI1_TX 55 -#define MEC1322_IRQ_SPI1_RX 56 -#define MEC1322_IRQ_GIRQ8 57 -#define MEC1322_IRQ_GIRQ9 58 -#define MEC1322_IRQ_GIRQ10 59 -#define MEC1322_IRQ_GIRQ11 60 -#define MEC1322_IRQ_GIRQ12 61 -#define MEC1322_IRQ_GIRQ13 62 -#define MEC1322_IRQ_GIRQ14 63 -#define MEC1322_IRQ_GIRQ15 64 -#define MEC1322_IRQ_GIRQ16 65 -#define MEC1322_IRQ_GIRQ17 66 -#define MEC1322_IRQ_GIRQ18 67 -#define MEC1322_IRQ_GIRQ19 68 -#define MEC1322_IRQ_GIRQ20 69 -#define MEC1322_IRQ_GIRQ21 70 -#define MEC1322_IRQ_GIRQ22 71 -#define MEC1322_IRQ_GIRQ23 72 -#define MEC1322_IRQ_DMA_8 81 -#define MEC1322_IRQ_DMA_9 82 -#define MEC1322_IRQ_DMA_10 83 -#define MEC1322_IRQ_DMA_11 84 -#define MEC1322_IRQ_PWM_WDT3 85 -#define MEC1322_IRQ_RTC 91 -#define MEC1322_IRQ_RTC_ALARM 92 - -/* Wake pin definitions, defined at board-level */ -#ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC -extern const enum gpio_signal hibernate_wake_pins[]; -extern const int hibernate_wake_pins_used; -#else -extern enum gpio_signal hibernate_wake_pins[]; -extern int hibernate_wake_pins_used; -#endif - -#endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c deleted file mode 100644 index bf3c7a9fb5..0000000000 --- a/chip/mec1322/spi.c +++ /dev/null @@ -1,171 +0,0 @@ -/* Copyright 2014 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* SPI master module for MEC1322 */ - -#include "common.h" -#include "console.h" -#include "dma.h" -#include "gpio.h" -#include "registers.h" -#include "spi.h" -#include "timer.h" -#include "util.h" -#include "hooks.h" -#include "task.h" - -#define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) - -#define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC) -#define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100 - -#define SPI_DMA_CHANNEL(port) (MEC1322_DMAC_SPI0_RX + (port)*2) - -/* only regular image needs mutex, LFW does not have scheduling */ -/* TODO: Move SPI locking to common code */ -#ifndef LFW -static struct mutex spi_mutex; -#endif - -static const struct dma_option spi_rx_option[] = { - { SPI_DMA_CHANNEL(0), (void *)&MEC1322_SPI_RD(0), - MEC1322_DMA_XFER_SIZE(1) }, - { SPI_DMA_CHANNEL(1), (void *)&MEC1322_SPI_RD(1), - MEC1322_DMA_XFER_SIZE(1) }, -}; - -static int wait_byte(const int port) -{ - timestamp_t deadline; - - deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US; - while ((MEC1322_SPI_SR(port) & 0x3) != 0x3) { - if (timestamp_expired(deadline, NULL)) - return EC_ERROR_TIMEOUT; - usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US); - } - return EC_SUCCESS; -} - -static int spi_tx(const int port, const uint8_t *txdata, int txlen) -{ - int i; - int ret = EC_SUCCESS; - uint8_t unused __attribute__((unused)) = 0; - - for (i = 0; i < txlen; ++i) { - MEC1322_SPI_TD(port) = txdata[i]; - ret = wait_byte(port); - if (ret != EC_SUCCESS) - return ret; - unused = MEC1322_SPI_RD(port); - } - - return ret; -} - -int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, uint8_t *rxdata, - int rxlen) -{ - int port = spi_device->port; - int ret = EC_SUCCESS; - - gpio_set_level(spi_device->gpio_cs, 0); - - /* Disable auto read */ - MEC1322_SPI_CR(port) &= ~BIT(5); - - ret = spi_tx(port, txdata, txlen); - if (ret != EC_SUCCESS) - return ret; - - /* Enable auto read */ - MEC1322_SPI_CR(port) |= BIT(5); - - if (rxlen != 0) { - dma_start_rx(&spi_rx_option[port], rxlen, rxdata); - MEC1322_SPI_TD(port) = 0; - } - return ret; -} - -int spi_transaction_flush(const struct spi_device_t *spi_device) -{ - int port = spi_device->port; - int ret = dma_wait(SPI_DMA_CHANNEL(port)); - uint8_t unused __attribute__((unused)) = 0; - - timestamp_t deadline; - - /* Disable auto read */ - MEC1322_SPI_CR(port) &= ~BIT(5); - - deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US; - /* Wait for FIFO empty SPISR_TXBE */ - while ((MEC1322_SPI_SR(port) & 0x01) != 0x1) { - if (timestamp_expired(deadline, NULL)) - return EC_ERROR_TIMEOUT; - usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US); - } - - dma_disable(SPI_DMA_CHANNEL(port)); - dma_clear_isr(SPI_DMA_CHANNEL(port)); - if (MEC1322_SPI_SR(port) & 0x2) - unused = MEC1322_SPI_RD(port); - - gpio_set_level(spi_device->gpio_cs, 1); - - return ret; -} - -int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, uint8_t *rxdata, - int rxlen) -{ - int ret; - -#ifndef LFW - mutex_lock(&spi_mutex); -#endif - ret = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen); - if (ret) - return ret; - ret = spi_transaction_flush(spi_device); - -#ifndef LFW - mutex_unlock(&spi_mutex); -#endif - return ret; -} - -int spi_enable(const struct spi_device_t *spi_device, int enable) -{ - int port = spi_device->port; - - if (enable) { - gpio_config_module(MODULE_SPI, 1); - - /* Set enable bit in SPI_AR */ - MEC1322_SPI_AR(port) |= 0x1; - - /* Set SPDIN to 0 -> Full duplex */ - MEC1322_SPI_CR(port) &= ~(0x3 << 2); - - /* Set CLKPOL, TCLKPH, RCLKPH to 0 */ - MEC1322_SPI_CC(port) &= ~0x7; - - /* Set LSBF to 0 -> MSB first */ - MEC1322_SPI_CR(port) &= ~0x1; - } else { - /* Clear enable bit in SPI_AR */ - MEC1322_SPI_AR(port) &= ~0x1; - - gpio_config_module(MODULE_SPI, 0); - } - - return EC_SUCCESS; -} diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c deleted file mode 100644 index 13fc2d9f81..0000000000 --- a/chip/mec1322/system.c +++ /dev/null @@ -1,393 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* System module for Chrome EC : MEC1322 hardware specific implementation */ - -#include "builtin/assert.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "gpio.h" -#include "host_command.h" -#include "registers.h" -#include "shared_mem.h" -#include "system.h" -#include "hooks.h" -#include "task.h" -#include "timer.h" -#include "usb_pd.h" -#include "util.h" -#include "spi.h" - -/* Indices for hibernate data registers (RAM backed by VBAT) */ -enum hibdata_index { - HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */ - HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */ - HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */ - HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */ - HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */ -}; - -static void check_reset_cause(void) -{ - uint32_t status = MEC1322_VBAT_STS; - uint32_t flags = 0; - uint32_t rst_sts = - MEC1322_PCR_CHIP_PWR_RST & - (MEC1322_PWR_RST_STS_VCC1 | MEC1322_PWR_RST_STS_VBAT); - - /* Clear the reset causes now that we've read them */ - MEC1322_VBAT_STS |= status; - MEC1322_PCR_CHIP_PWR_RST |= rst_sts; - - /* - * BIT[6] determine VCC1 reset - */ - if (rst_sts & MEC1322_PWR_RST_STS_VCC1) - flags |= EC_RESET_FLAG_RESET_PIN; - - flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS); - MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0; - - if ((status & MEC1322_VBAT_STS_WDT) && - !(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD | - EC_RESET_FLAG_HIBERNATE))) - flags |= EC_RESET_FLAG_WATCHDOG; - - system_set_reset_flags(flags); -} - -int system_is_reboot_warm(void) -{ - uint32_t reset_flags; - /* - * Check reset cause here, - * gpio_pre_init is executed faster than system_pre_init - */ - check_reset_cause(); - reset_flags = system_get_reset_flags(); - - if ((reset_flags & EC_RESET_FLAG_RESET_PIN) || - (reset_flags & EC_RESET_FLAG_POWER_ON) || - (reset_flags & EC_RESET_FLAG_WATCHDOG) || - (reset_flags & EC_RESET_FLAG_HARD) || - (reset_flags & EC_RESET_FLAG_SOFT) || - (reset_flags & EC_RESET_FLAG_HIBERNATE)) - return 0; - else - return 1; -} - -void system_pre_init(void) -{ - /* Enable direct NVIC */ - MEC1322_EC_INT_CTRL |= 1; - - /* Disable ARM TRACE debug port */ - MEC1322_EC_TRACE_EN &= ~1; - - /* Deassert nSIO_RESET */ - MEC1322_PCR_PWR_RST_CTL &= ~BIT(0); - - spi_enable(SPI_FLASH_DEVICE, 1); -} - -void chip_save_reset_flags(uint32_t flags) -{ - MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = flags; -} - -uint32_t chip_read_reset_flags(void) -{ - return MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS); -} - -noreturn void _system_reset(int flags, int wake_from_hibernate) -{ - uint32_t save_flags = 0; - - /* Disable interrupts to avoid task swaps during reboot */ - interrupt_disable(); - - /* Save current reset reasons if necessary */ - if (flags & SYSTEM_RESET_PRESERVE_FLAGS) - save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED; - - if (flags & SYSTEM_RESET_LEAVE_AP_OFF) - save_flags |= EC_RESET_FLAG_AP_OFF; - - if (wake_from_hibernate) - save_flags |= EC_RESET_FLAG_HIBERNATE; - else if (flags & SYSTEM_RESET_HARD) - save_flags |= EC_RESET_FLAG_HARD; - else - save_flags |= EC_RESET_FLAG_SOFT; - - chip_save_reset_flags(save_flags); - - /* Trigger watchdog in 1ms */ - MEC1322_WDG_LOAD = 1; - MEC1322_WDG_CTL |= 1; - - /* Spin and wait for reboot; should never return */ - while (1) - ; -} - -void system_reset(int flags) -{ - _system_reset(flags, 0); -} - -const char *system_get_chip_vendor(void) -{ - return "smsc"; -} - -const char *system_get_chip_name(void) -{ - switch (MEC1322_CHIP_DEV_ID) { - case 0x15: - return "mec1322"; - default: - return "unknown"; - } -} - -static char to_hex(int x) -{ - if (x >= 0 && x <= 9) - return '0' + x; - return 'a' + x - 10; -} - -const char *system_get_chip_revision(void) -{ - static char buf[3]; - uint8_t rev = MEC1322_CHIP_DEV_REV; - - buf[0] = to_hex(rev / 16); - buf[1] = to_hex(rev & 0xf); - buf[2] = '\0'; - return buf; -} - -static int bbram_idx_lookup(enum system_bbram_idx idx) -{ - switch (idx) { - case SYSTEM_BBRAM_IDX_PD0: - return HIBDATA_INDEX_PD0; - case SYSTEM_BBRAM_IDX_PD1: - return HIBDATA_INDEX_PD1; - case SYSTEM_BBRAM_IDX_PD2: - return HIBDATA_INDEX_PD2; - default: - return -1; - } -} - -int system_get_bbram(enum system_bbram_idx idx, uint8_t *value) -{ - int hibdata = bbram_idx_lookup(idx); - - if (hibdata < 0) - return EC_ERROR_UNIMPLEMENTED; - - *value = MEC1322_VBAT_RAM(hibdata); - return EC_SUCCESS; -} - -int system_set_bbram(enum system_bbram_idx idx, uint8_t value) -{ - int hibdata = bbram_idx_lookup(idx); - - if (hibdata < 0) - return EC_ERROR_UNIMPLEMENTED; - - MEC1322_VBAT_RAM(hibdata) = value; - return EC_SUCCESS; -} - -int system_set_scratchpad(uint32_t value) -{ - MEC1322_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD) = value; - return EC_SUCCESS; -} - -int system_get_scratchpad(uint32_t *value) -{ - *value = MEC1322_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD); - return EC_SUCCESS; -} - -void system_hibernate(uint32_t seconds, uint32_t microseconds) -{ - int i; - -#ifdef CONFIG_HOSTCMD_PD - /* Inform the PD MCU that we are going to hibernate. */ - host_command_pd_request_hibernate(); - /* Wait to ensure exchange with PD before hibernating. */ - msleep(100); -#endif - - cflush(); - - if (board_hibernate) - board_hibernate(); - - /* Disable interrupts */ - interrupt_disable(); - for (i = 0; i <= 92; ++i) { - task_disable_irq(i); - task_clear_pending_irq(i); - } - - for (i = 8; i <= 23; ++i) - MEC1322_INT_DISABLE(i) = 0xffffffff; - - MEC1322_INT_BLK_DIS |= 0xffff00; - - /* Power down ADC VREF */ - MEC1322_EC_ADC_VREF_PD |= 1; - - /* Assert nSIO_RESET */ - MEC1322_PCR_PWR_RST_CTL |= 1; - - /* Disable UART */ - MEC1322_UART_ACT &= ~0x1; - MEC1322_LPC_ACT &= ~0x1; - - /* Disable JTAG */ - MEC1322_EC_JTAG_EN &= ~1; - - /* Disable 32KHz clock */ - MEC1322_VBAT_CE &= ~0x2; - - /* Stop watchdog */ - MEC1322_WDG_CTL &= ~1; - - /* Stop timers */ - MEC1322_TMR32_CTL(0) &= ~1; - MEC1322_TMR32_CTL(1) &= ~1; - MEC1322_TMR16_CTL(0) &= ~1; - - /* Power down ADC */ - MEC1322_ADC_CTRL &= ~1; - - /* Disable blocks */ - MEC1322_PCR_CHIP_SLP_EN |= 0x3; - MEC1322_PCR_EC_SLP_EN |= MEC1322_PCR_EC_SLP_EN_SLEEP; - MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP; - MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP; - MEC1322_PCR_SLOW_CLK_CTL &= 0xfffffc00; - - /* Set sleep state */ - MEC1322_PCR_SYS_SLP_CTL = (MEC1322_PCR_SYS_SLP_CTL & ~0x7) | 0x2; - CPU_SCB_SYSCTRL |= 0x4; - - /* Setup GPIOs for hibernate */ - if (board_hibernate_late) - board_hibernate_late(); - -#ifdef CONFIG_USB_PD_PORT_MAX_COUNT - /* - * Leave USB-C charging enabled in hibernate, in order to - * allow wake-on-plug. 5V enable must be pulled low. - */ - switch (board_get_usb_pd_port_count()) { -#if CONFIG_USB_PD_PORT_MAX_COUNT >= 2 - case 2: - gpio_set_flags(GPIO_USB_C1_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT); - gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 0); - /* Fall through */ -#endif -#if CONFIG_USB_PD_PORT_MAX_COUNT >= 1 - case 1: - gpio_set_flags(GPIO_USB_C0_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT); - gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 0); - /* Fall through */ -#endif - case 0: - /* Nothing to do but break */ - break; - default: - /* More ports needs to be defined */ - ASSERT(false); - break; - } -#endif /* CONFIG_USB_PD_PORT_MAX_COUNT */ - - if (hibernate_wake_pins_used > 0) { - for (i = 0; i < hibernate_wake_pins_used; ++i) { - const enum gpio_signal pin = hibernate_wake_pins[i]; - - gpio_reset(pin); - gpio_enable_interrupt(pin); - } - - interrupt_enable(); - task_enable_irq(MEC1322_IRQ_GIRQ8); - task_enable_irq(MEC1322_IRQ_GIRQ9); - task_enable_irq(MEC1322_IRQ_GIRQ10); - task_enable_irq(MEC1322_IRQ_GIRQ11); - task_enable_irq(MEC1322_IRQ_GIRQ20); - } - - if (seconds || microseconds) { - MEC1322_INT_BLK_EN |= BIT(17); - MEC1322_INT_ENABLE(17) |= BIT(20); - interrupt_enable(); - task_enable_irq(MEC1322_IRQ_HTIMER); - if (seconds > 2) { - ASSERT(seconds <= 0xffff / 8); - MEC1322_HTIMER_CONTROL = 1; - MEC1322_HTIMER_PRELOAD = - (seconds * 8 + microseconds / 125000); - } else { - MEC1322_HTIMER_CONTROL = 0; - MEC1322_HTIMER_PRELOAD = - (seconds * 1000000 + microseconds) * 2 / 71; - } - } - - cpu_enter_suspend_mode(); - - /* Use 48MHz clock to speed through wake-up */ - MEC1322_PCR_PROC_CLK_CTL = 1; - - /* Reboot */ - _system_reset(0, 1); - - /* We should never get here. */ - while (1) - ; -} - -static void htimer_interrupt(void) -{ - /* Time to wake up */ -} -DECLARE_IRQ(MEC1322_IRQ_HTIMER, htimer_interrupt, 1); - -enum ec_image system_get_shrspi_image_copy(void) -{ - return MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX); -} - -uint32_t system_get_lfw_address(void) -{ - uint32_t *const lfw_vector = - (uint32_t *const)CONFIG_PROGRAM_MEMORY_BASE; - - return *(lfw_vector + 1); -} - -void system_set_image_copy(enum ec_image copy) -{ - MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = - (copy == EC_IMAGE_RW) ? EC_IMAGE_RW : EC_IMAGE_RO; -} diff --git a/chip/mec1322/uart.c b/chip/mec1322/uart.c deleted file mode 100644 index a913cf36ab..0000000000 --- a/chip/mec1322/uart.c +++ /dev/null @@ -1,219 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* UART module for MEC1322 */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "lpc.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "uart.h" -#include "util.h" - -#define TX_FIFO_SIZE 16 - -static int init_done; -static int tx_fifo_used; - -int uart_init_done(void) -{ - return init_done; -} - -void uart_tx_start(void) -{ - /* If interrupt is already enabled, nothing to do */ - if (MEC1322_UART_IER & BIT(1)) - return; - - /* Do not allow deep sleep while transmit in progress */ - disable_sleep(SLEEP_MASK_UART); - - /* - * Re-enable the transmit interrupt, then forcibly trigger the - * interrupt. This works around a hardware problem with the - * UART where the FIFO only triggers the interrupt when its - * threshold is _crossed_, not just met. - */ - MEC1322_UART_IER |= BIT(1); - task_trigger_irq(MEC1322_IRQ_UART); -} - -void uart_tx_stop(void) -{ - MEC1322_UART_IER &= ~BIT(1); - - /* Re-allow deep sleep */ - enable_sleep(SLEEP_MASK_UART); -} - -void uart_tx_flush(void) -{ - /* Wait for transmit FIFO empty */ - while (!(MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY)) - ; -} - -int uart_tx_ready(void) -{ - /* - * We have no indication of free space in transmit FIFO. To work around - * this, we check transmit FIFO empty bit every 16 characters written. - */ - return tx_fifo_used != 0 || (MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY); -} - -int uart_tx_in_progress(void) -{ - /* return 0: FIFO is empty, 1: FIFO NOT Empty */ - return !(MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY); -} - -int uart_rx_available(void) -{ - return MEC1322_UART_LSR & BIT(0); -} - -void uart_write_char(char c) -{ - /* Wait for space in transmit FIFO. */ - while (!uart_tx_ready()) - ; - - tx_fifo_used = (tx_fifo_used + 1) % TX_FIFO_SIZE; - MEC1322_UART_TB = c; -} - -int uart_read_char(void) -{ - return MEC1322_UART_RB; -} - -static void uart_clear_rx_fifo(int channel) -{ - MEC1322_UART_FCR = BIT(0) | BIT(1); -} - -/** - * Interrupt handler for UART - */ -static void uart_ec_interrupt(void) -{ - /* Read input FIFO until empty, then fill output FIFO */ - uart_process_input(); - uart_process_output(); -} -DECLARE_IRQ(MEC1322_IRQ_UART, uart_ec_interrupt, 1); - -void uart_init(void) -{ - /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MEC1322_UART_CFG &= ~BIT(1); - - /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ - - /* Set CLK_SRC = 0 */ - MEC1322_UART_CFG &= ~BIT(0); - - /* Set DLAB = 1 */ - MEC1322_UART_LCR |= BIT(7); - - /* PBRG0/PBRG1 */ - MEC1322_UART_PBRG0 = 1; - MEC1322_UART_PBRG1 = 0; - - /* Set DLAB = 0 */ - MEC1322_UART_LCR &= ~BIT(7); - - /* Set word length to 8-bit */ - MEC1322_UART_LCR |= BIT(0) | BIT(1); - - /* Enable FIFO */ - MEC1322_UART_FCR = BIT(0); - - /* Activate UART */ - MEC1322_UART_ACT |= BIT(0); - - /* - clock_enable_peripheral(CGC_OFFSET_UART, mask, - CGC_MODE_RUN | CGC_MODE_SLEEP);*/ - - gpio_config_module(MODULE_UART, 1); - - /* - * Enable interrupts for UART0. - */ - uart_clear_rx_fifo(0); - MEC1322_UART_IER |= BIT(0); - MEC1322_UART_MCR |= BIT(3); - MEC1322_INT_ENABLE(15) |= BIT(0); - MEC1322_INT_BLK_EN |= BIT(15); - task_enable_irq(MEC1322_IRQ_UART); - - init_done = 1; -} - -#ifdef CONFIG_LOW_POWER_IDLE -void uart_enter_dsleep(void) -{ - /* Disable the UART interrupt. */ - task_disable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART=13 */ - - /* - * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt - * with the flags defined in the gpio.inc file. - */ - gpio_reset(GPIO_UART0_RX); - - /* power-down/de-activate UART0 */ - MEC1322_UART_ACT &= ~BIT(0); - - /* Clear pending interrupts on GPIO_UART0_RX(GPIO162, girq=8, bit=18) */ - MEC1322_INT_SOURCE(8) = (1 << 18); - - /* Enable GPIO interrupts on the UART0 RX pin. */ - gpio_enable_interrupt(GPIO_UART0_RX); -} - -void uart_exit_dsleep(void) -{ - /* - * If the UART0 RX GPIO interrupt has not fired, then no edge has been - * detected. Disable the GPIO interrupt so that switching the pin over - * to a UART pin doesn't inadvertently cause a GPIO edge interrupt. - * Note: we can't disable this interrupt if it has already fired - * because then the IRQ will not run at all. - */ - if (!(BIT(18) & MEC1322_INT_SOURCE(8))) /* if edge interrupt */ - gpio_disable_interrupt(GPIO_UART0_RX); - - /* Configure UART0 pins for use in UART peripheral. */ - gpio_config_module(MODULE_UART, 1); - - /* Clear pending interrupts on UART peripheral and enable interrupts. */ - uart_clear_rx_fifo(0); - task_enable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART = 13 */ - - /* power-up/activate UART0 */ - MEC1322_UART_ACT |= BIT(0); -} - -void uart_deepsleep_interrupt(enum gpio_signal signal) -{ - /* - * Activity seen on UART RX pin while UART was disabled for deep sleep. - * The console won't see that character because the UART is disabled, - * so we need to inform the clock module of UART activity ourselves. - */ - clock_refresh_console_in_use(); - - /* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */ - gpio_disable_interrupt(GPIO_UART0_RX); -} -#endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/mec1322/util/pack_ec.py b/chip/mec1322/util/pack_ec.py deleted file mode 100755 index 9062621c9a..0000000000 --- a/chip/mec1322/util/pack_ec.py +++ /dev/null @@ -1,348 +0,0 @@ -#!/usr/bin/env python3 - -# Copyright 2013 The ChromiumOS Authors -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# A script to pack EC binary into SPI flash image for MEC1322 -# Based on MEC1322_ROM_Doc_Rev0.5.pdf. - -import argparse -import hashlib -import os -import struct -import subprocess -import tempfile - -LOAD_ADDR = 0x100000 -HEADER_SIZE = 0x140 -SPI_CLOCK_LIST = [48, 24, 12, 8] -SPI_READ_CMD_LIST = [0x3, 0xB, 0x3B] - -CRC_TABLE = [ - 0x00, - 0x07, - 0x0E, - 0x09, - 0x1C, - 0x1B, - 0x12, - 0x15, - 0x38, - 0x3F, - 0x36, - 0x31, - 0x24, - 0x23, - 0x2A, - 0x2D, -] - - -def Crc8(crc, data): - """Update CRC8 value.""" - for v in data: - crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]) - crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xF)]) - return crc ^ 0x55 - - -def GetEntryPoint(payload_file): - """Read entry point from payload EC image.""" - with open(payload_file, "rb") as f: - f.seek(4) - s = f.read(4) - return struct.unpack("<I", s)[0] - - -def GetPayloadFromOffset(payload_file, offset): - """Read payload and pad it to 64-byte aligned.""" - with open(payload_file, "rb") as f: - f.seek(offset) - payload = bytearray(f.read()) - rem_len = len(payload) % 64 - if rem_len: - payload += b"\0" * (64 - rem_len) - return payload - - -def GetPayload(payload_file): - """Read payload and pad it to 64-byte aligned.""" - return GetPayloadFromOffset(payload_file, 0) - - -def GetPublicKey(pem_file): - """Extract public exponent and modulus from PEM file.""" - result = subprocess.run( - ["openssl", "rsa", "-in", pem_file, "-text", "-noout"], - stdout=subprocess.PIPE, - encoding="utf-8", - ) - modulus_raw = [] - in_modulus = False - for line in result.stdout.splitlines(): - if line.startswith("modulus"): - in_modulus = True - elif not line.startswith(" "): - in_modulus = False - elif in_modulus: - modulus_raw.extend(line.strip().strip(":").split(":")) - if line.startswith("publicExponent"): - exp = int(line.split(" ")[1], 10) - modulus_raw.reverse() - modulus = bytearray((int(x, 16) for x in modulus_raw[:256])) - return struct.pack("<Q", exp), modulus - - -def GetSpiClockParameter(args): - assert args.spi_clock in SPI_CLOCK_LIST, ( - "Unsupported SPI clock speed %d MHz" % args.spi_clock - ) - return SPI_CLOCK_LIST.index(args.spi_clock) - - -def GetSpiReadCmdParameter(args): - assert args.spi_read_cmd in SPI_READ_CMD_LIST, ( - "Unsupported SPI read command 0x%x" % args.spi_read_cmd - ) - return SPI_READ_CMD_LIST.index(args.spi_read_cmd) - - -def PadZeroTo(data, size): - data.extend(b"\0" * (size - len(data))) - - -def BuildHeader(args, payload_len, rorofile): - # Identifier and header version - header = bytearray(b"CSMS\0") - - PadZeroTo(header, 0x6) - header.append(GetSpiClockParameter(args)) - header.append(GetSpiReadCmdParameter(args)) - - header.extend(struct.pack("<I", LOAD_ADDR)) - header.extend(struct.pack("<I", GetEntryPoint(rorofile))) - header.append((payload_len >> 6) & 0xFF) - header.append((payload_len >> 14) & 0xFF) - PadZeroTo(header, 0x14) - header.extend(struct.pack("<I", args.payload_offset)) - - exp, modulus = GetPublicKey(args.payload_key) - PadZeroTo(header, 0x20) - header.extend(exp) - PadZeroTo(header, 0x30) - header.extend(modulus) - PadZeroTo(header, HEADER_SIZE) - - return header - - -def SignByteArray(data, pem_file): - hash_file = tempfile.mkstemp(prefix="pack_ec.")[1] - sign_file = tempfile.mkstemp(prefix="pack_ec.")[1] - try: - with open(hash_file, "wb") as f: - hasher = hashlib.sha256() - hasher.update(data) - f.write(hasher.digest()) - subprocess.run( - [ - "openssl", - "rsautl", - "-sign", - "-inkey", - pem_file, - "-keyform", - "PEM", - "-in", - hash_file, - "-out", - sign_file, - ], - check=True, - ) - with open(sign_file, "rb") as f: - signed = f.read() - return bytearray(reversed(signed)) - finally: - os.remove(hash_file) - os.remove(sign_file) - - -def BuildTag(args): - tag = bytearray( - [ - (args.header_loc >> 8) & 0xFF, - (args.header_loc >> 16) & 0xFF, - (args.header_loc >> 24) & 0xFF, - ] - ) - if args.chip_select != 0: - tag[2] |= 0x80 - tag.append(Crc8(0, tag)) - return tag - - -def PacklfwRoImage(rorw_file, loader_file, image_size): - """TODO:Clean up to get rid of Temp file and just use memory - to save data""" - """Create a temp file with the - first image_size bytes from the rorw file and the - bytes from the loader_file appended - return the filename""" - fo = tempfile.NamedTemporaryFile(delete=False) # Need to keep file around - with open(loader_file, "rb") as fin1: - pro = fin1.read() - fo.write(pro) - with open(rorw_file, "rb") as fin: - ro = fin.read(image_size) - fo.write(ro) - fo.close() - return fo.name - - -def parseargs(): - parser = argparse.ArgumentParser() - parser.add_argument( - "-i", - "--input", - help="EC binary to pack, usually ec.bin or ec.RO.flat.", - metavar="EC_BIN", - default="ec.bin", - ) - parser.add_argument( - "-o", - "--output", - help="Output flash binary file", - metavar="EC_SPI_FLASH", - default="ec.packed.bin", - ) - parser.add_argument( - "--header_key", - help="PEM key file for signing header", - default="rsakey_sign_header.pem", - ) - parser.add_argument( - "--payload_key", - help="PEM key file for signing payload", - default="rsakey_sign_payload.pem", - ) - parser.add_argument( - "--loader_file", help="EC loader binary", default="ecloader.bin" - ) - parser.add_argument( - "-s", - "--spi_size", - type=int, - help="Size of the SPI flash in MB", - default=4, - ) - parser.add_argument( - "-l", - "--header_loc", - type=int, - help="Location of header in SPI flash", - default=0x170000, - ) - parser.add_argument( - "-p", - "--payload_offset", - type=int, - help="The offset of payload from the header", - default=0x240, - ) - parser.add_argument( - "-r", - "--rwpayload_loc", - type=int, - help="The offset of payload from the header", - default=0x190000, - ) - parser.add_argument( - "-z", - "--romstart", - type=int, - help="The first location to output of the rom", - default=0, - ) - parser.add_argument( - "-c", - "--chip_select", - type=int, - help="Chip select signal to use, either 0 or 1.", - default=0, - ) - parser.add_argument( - "--spi_clock", - type=int, - help="SPI clock speed. 8, 12, 24, or 48 MHz.", - default=24, - ) - parser.add_argument( - "--spi_read_cmd", - type=int, - help="SPI read command. 0x3, 0xB, or 0x3B.", - default=0xB, - ) - parser.add_argument( - "--image_size", - type=int, - help="Size of a single image.", - default=(96 * 1024), - ) - return parser.parse_args() - - -def main(): - args = parseargs() - - spi_size = args.spi_size * 1024 - args.header_loc = spi_size - (128 * 1024) - args.rwpayload_loc = spi_size - (256 * 1024) - args.romstart = spi_size - (256 * 1024) - - spi_list = [] - - rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size) - payload = GetPayload(rorofile) - payload_len = len(payload) - payload_signature = SignByteArray(payload, args.payload_key) - header = BuildHeader(args, payload_len, rorofile) - header_signature = SignByteArray(header, args.header_key) - tag = BuildTag(args) - # truncate the RW to 128k - payloadrw = GetPayloadFromOffset(args.input, args.image_size)[: 128 * 1024] - os.remove(rorofile) # clean up the temp file - - spi_list.append((args.header_loc, header, "header")) - spi_list.append( - (args.header_loc + HEADER_SIZE, header_signature, "header_signature") - ) - spi_list.append((args.header_loc + args.payload_offset, payload, "payload")) - spi_list.append( - ( - args.header_loc + args.payload_offset + payload_len, - payload_signature, - "payload_signature", - ) - ) - spi_list.append((spi_size - 256, tag, "tag")) - spi_list.append((args.rwpayload_loc, payloadrw, "payloadrw")) - - spi_list = sorted(spi_list) - - with open(args.output, "wb") as f: - addr = args.romstart - for s in spi_list: - assert addr <= s[0] - if addr < s[0]: - f.write(b"\xff" * (s[0] - addr)) - addr = s[0] - f.write(s[1]) - addr += len(s[1]) - if addr < spi_size: - f.write(b"\xff" * (spi_size - addr)) - - -if __name__ == "__main__": - main() diff --git a/chip/mec1322/util/rsakey_sign_header.pem b/chip/mec1322/util/rsakey_sign_header.pem deleted file mode 100644 index 37799ebbec..0000000000 --- a/chip/mec1322/util/rsakey_sign_header.pem +++ /dev/null @@ -1,28 +0,0 @@ ------BEGIN PRIVATE KEY----- -MIIEvwIBADANBgkqhkiG9w0BAQEFAASCBKkwggSlAgEAAoIBAQCd0knJ+sVzkO40 -g7VguqpqrmwqgYPfgq3m7GHGitWgxjM/JDpKaOvq4G9O+yYUD/75V5GZJkRY0iE8 -MJCCvSkyoFHcCP0jvma9G/c13wXfLPGUunrJnV+Wzwy5+S1MXdax532gK9qeUmOB -HpIttkFRl3qhVHu9to2dbsx1S/AIA0GIPAINkcZxfRCAcheIoqK/oMqse+EDS9Zm -6frha9oS1+iRlqMPYKrOgWTKnkY3H/4M/HFj90hVzxun3qQj0mo3EdYoSrbCnyjG -JNjnuCdSEODmG5+FCTVWCfl/AolYmOWjMfCnfX7/HlfhOY+fOR91FKrgOjWHHf3a -0FhdUZDNAgMBAAECggEBAJKea6j2jXu42GP3PIk5wdrMYnb2zeHXEOJpFskR8Dem -CrQNXw4D/bC+gwo4Lv8SgUl6PiyurW5rAS9e2tJrFBwRbxthSnNrjxz/HyJwKI9W -vLT0reAikUyU3Hjl8lxxDWVH76DfPQI6/nBVS26mVHaNqQK6bx8nutbYuZ/7RWra -zatdjrl29D0E/xTva0S4AUPI7DmflwS6YbfVlTsyhnwphaEwD7eCDhD9h4nGQG8z -0WKDN2X1F7CmjrK9fy7SCHO9SKc3WNSjp2Dc0ImF2k72Mfw5jtOs81lczktztPy0 -gv4x6Tg0ws4Et9eI6Ub80tAZ+wQ5Vj+wzExMOp4K5KECgYEA0jz5IsRmie6y/WRG -6dI98nnyLoISIQue8xOA5J/OUyYfHn9CgJvGslRVg2mmSQ9GPkaMIN0dADvB6Tsh -XelAZZjnAo8pSyahz3OdcdgP6xksMjtKReXiLqu0ntfQS42nQDYNvRd2/clrYYRN -SlijT53QMqI4DSMz+0rLqUwvRskCgYEAwCyEEJ1Z/CI2ONN1tIEnJSuzZRYxlwNL -mVXx03ZSVi+L2MOMJjiCoeUZ/MVSacW+Elg6aU3U1GdOhNfQaPZJNqISACtm314Y -Xi9bMXegyQp3uBRnEah82ejm8hloOAOKZNgbqgt9o6FDrsccw3udIgzsgPY4koUK -1fNrDPJ5x+UCgYBwlEH8whr+hZnHYqkukGynqXFsQi6fD3AATlNZGdIMaH+FfzQH -VmNiHxLjmfF3cfx1YKWs+3qKI3XFBOrrNPpM7UHW9v5vxbIkOo725XIwvHwUMfel -0mH6B+ximsJpkuMa2VcmCKipYfBkecpBo5FgEuvoEUHelxlA2V6Ru8AdMQKBgQC/ -uanoiZQFIHzIJPABrfjH9Nl9uK6w4vDBgiVJu3pZ0gXLtQxV9Xse2dsbfCHEtSv0 -UWG1PZlgb9C+aDHdBhn1D6y1zpdLsizNiqGIsLkQ2gim9nP+AgLNxLbkQsTfXWjt -Q04WUHCAl5tW+/+OZ/1Uw2ARKZU3WNR+r+PVfvRQoQKBgQCjksWLe3Zx2yxnUenz -vaY09UTt42rawbUkm+xpNzOt7K1TudRODe444XG9fFgkNa5HPiAENoZ91Jv223x8 -Fi2SjfGA6/r/J1ash4cDcJLogTEP27YyJyhwXZFKtjfFeD3e2hvcMFMDG4EBHHXd -Bv/r6+6E+f30Y4bN3ZgK/rN6Tg== ------END PRIVATE KEY----- diff --git a/chip/mec1322/util/rsakey_sign_payload.pem b/chip/mec1322/util/rsakey_sign_payload.pem deleted file mode 100644 index 6845097749..0000000000 --- a/chip/mec1322/util/rsakey_sign_payload.pem +++ /dev/null @@ -1,28 +0,0 @@ ------BEGIN PRIVATE KEY----- -MIIEvQIBADANBgkqhkiG9w0BAQEFAASCBKcwggSjAgEAAoIBAQDQaeNJ6+a/KXhs -/0Xa2coG+4d+pc+4qs4O/6caxAtzr1YP155C4QxqfZw0DETreK7K/kgSgOJ6Q1gW -Yo88Fb4foxVYJbV2Bb+mdNlaHP/o6TrvBmqdsIjP5u1FwtmjquaewL2E3T4rHCXl -QgM7AQXAFzKt2HeaMeHvC2t+x/AganhfztOpqhGTL6lHiLC55SPNkWCb3GokotbL -Ul7q+wLSTpKS0vNuigjGVBVuV7YrwWhehOoLuV5FDMXHlMTemYH6+V5j78ZtSrXm -0RmKAKXoO+HbKbgALICUw5kzxXLSAoHx2rXLlou9I00olxsWir1lokxaWa1La3wA -pr214pxXAgMBAAECggEAdsXxrz4OeaEDrXJpeAioNwR/unB6ie5lkmyl6f4R3LLu -5AZofgrNTZ8aNxtK57sWOj9iCZGEAFOCzvcKVB68BEGnt11+Ja2vBAkRmWZvfWf1 -myTX+9gQkBM144zhBYIu/ggvuZlwhZb8DcRqHOU/RrKxwhtcRfbpoJasg0skkQO0 -bU2hwSu4kM+T2diyXp4V1PR4vrxZPNQ+B8sWxWKJs58+3NdWswwe9NcFQla0QTFz -7MIlMJNlJgTXjSYC8TjDlBlevwE5HoikpfSSvFr4uouyfpfWBxNFd8Tm/yFSTUqY -XO3oyU/NLK+BN7Sxj6Cs1Fx65yhMCmsqGQqCNOz2OQKBgQD4gIF6vVduyKfPV3EE -4lhFktlFRXeR+z9LXpGth3vwNN0XpPql1jr8hYPQqpSKefZRF5r8hLjt2ZaLDbnb -iVYwHxbXRuF5P6qsaSy1uVYG4og5LV5ddSBzf+/MhDInQk/O5tdvOrgQfcJzRJRg -MSx5uzs66r8/AFKCVTB/ptNgzQKBgQDWs7qqaHNHGRRfegRhwkkDvhRAMQKWsgL7 -kTWw/qW+b8mRYhCC4JvbU+OeFkf5kejGpFgDuvB4eH+rsPRVU8jSWZXrMKjGdZN1 -T6fFa5vz1VsRNhiVU3F2jfXTY5t7qQ18jEoMQxGxdGJy52Py+3N34ZWNS4cifLNS -rYjZnQmhswKBgD3rd1foGgMmyHmnpie7ZpdfcfgKyTJ80larZ80/dyhxY63ik/oC -mYwWkLPL7Vtb7H5kTWAiihnqH9LiRq9nVyyCcqSNqt0VeiefxV46oi7w/1SP83WC -G+XruQrS3dRed5hseL3kebzSOUOTkQ0u85AZkTarC6BdKjIDnCQSo5T5AoGAKNep -087o1waTVJJOkRY3c4nOKmPoXShh3t9BunjGqNJ1Ir3n7C20GGX9783HRVeXU2ph -/9uo8RHjH5Ma97xngHRgS4xHHvGw6mkLvkd5NEpK95w10vo7pFTfBaZ2JnEDSsUZ -NPnxPLOqIreX0No6nfyAyY8rlsjoB/tRBCyWb3cCgYEAgzJCllzahDvgCbmjI9Km -h7mUVc5U2fQR5B/WRa5iTSlQd+O4TXna7ZCxKDyYlesSBAiKanX0669Iri6cu4S6 -gMc7MJmm3VrnZGXoukSv3Zyot+hkaFrZTrXAIQiuYDK6YC5OK7kqM+DqtJOWUsfg -itdiqPKeYtViDQkxqJ1nkSw= ------END PRIVATE KEY----- diff --git a/chip/mec1322/watchdog.c b/chip/mec1322/watchdog.c deleted file mode 100644 index a072e86e76..0000000000 --- a/chip/mec1322/watchdog.c +++ /dev/null @@ -1,103 +0,0 @@ -/* Copyright 2013 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Watchdog driver */ - -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "watchdog.h" - -void watchdog_reload(void) -{ - MEC1322_WDG_KICK = 1; - -#ifdef CONFIG_WATCHDOG_HELP - /* Reload the auxiliary timer */ - MEC1322_TMR16_CTL(0) &= ~BIT(5); - MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MEC1322_TMR16_CTL(0) |= BIT(5); -#endif -} -DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); - -int watchdog_init(void) -{ -#ifdef CONFIG_WATCHDOG_HELP - uint32_t val; - - /* - * Watchdog does not warn us before expiring. Let's use a 16-bit - * timer as an auxiliary timer. - */ - - /* Stop the auxiliary timer if it's running */ - MEC1322_TMR16_CTL(0) &= ~BIT(5); - - /* Enable auxiliary timer */ - MEC1322_TMR16_CTL(0) |= BIT(0); - - val = MEC1322_TMR16_CTL(0); - - /* Pre-scale = 48000 -> 1kHz -> Period = 1ms */ - val = (val & 0xffff) | (47999 << 16); - - /* No auto restart */ - val &= ~BIT(3); - - /* Count down */ - val &= ~BIT(2); - - MEC1322_TMR16_CTL(0) = val; - - /* Enable interrupt from auxiliary timer */ - MEC1322_TMR16_IEN(0) |= 1; - task_enable_irq(MEC1322_IRQ_TIMER16_0); - MEC1322_INT_ENABLE(23) |= BIT(0); - MEC1322_INT_BLK_EN |= BIT(23); - - /* Load and start the auxiliary timer */ - MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MEC1322_TMR16_CNT(0) |= BIT(5); -#endif - - /* Set timeout. It takes 1007us to decrement WDG_CNT by 1. */ - MEC1322_WDG_LOAD = CONFIG_WATCHDOG_PERIOD_MS * 1000 / 1007; - - /* Start watchdog */ - MEC1322_WDG_CTL |= 1; - - return EC_SUCCESS; -} - -#ifdef CONFIG_WATCHDOG_HELP -void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp) -{ - /* Clear status */ - MEC1322_TMR16_STS(0) |= 1; - - watchdog_trace(excep_lr, excep_sp); -} - -void IRQ_HANDLER(MEC1322_IRQ_TIMER16_0)(void) __attribute__((naked)); -void IRQ_HANDLER(MEC1322_IRQ_TIMER16_0)(void) -{ - /* Naked call so we can extract raw LR and SP */ - asm volatile("mov r0, lr\n" - "mov r1, sp\n" - /* Must push registers in pairs to keep 64-bit aligned - * stack for ARM EABI. This also conveninently saves - * R0=LR so we can pass it to task_resched_if_needed. */ - "push {r0, lr}\n" - "bl watchdog_check\n" - "pop {r0, lr}\n" - "b task_resched_if_needed\n"); -} -const struct irq_priority __keep IRQ_PRIORITY(MEC1322_IRQ_TIMER16_0) - __attribute__((section(".rodata.irqprio"))) = { MEC1322_IRQ_TIMER16_0, - 0 }; /* put the watchdog - at the highest - priority */ -#endif diff --git a/include/fan.h b/include/fan.h index 946d0607c9..31af7a58ff 100644 --- a/include/fan.h +++ b/include/fan.h @@ -119,7 +119,7 @@ int fan_is_stalled(int ch); * even when duty is already in upper/lower bound. Then this action won't work, * and fan_status will be marked as FRUSTRATED. * - * For other implementations in chip layer (mchp and mec1322), there is no + * For other implementations in chip layer (mchp), there is no * changing period. So they don't have CHANGING status. * Just return status as LOCKED in normal spinning case, return STOPPED when * not spinning, return FRUSTRATED when the related flags (which is read from diff --git a/util/compare_build.sh b/util/compare_build.sh index e70dcdbed2..10399d410b 100755 --- a/util/compare_build.sh +++ b/util/compare_build.sh @@ -22,7 +22,6 @@ # * ish - " # * it83xx - " # * lm4 - " -# * mec1322 - " # * max32660 - " # * mt_scp - " # @@ -133,7 +132,6 @@ parse-boards() { [ish]="$(boards-with 'CHIP[[:space:]:=]*ish')" [it83xx]="$(boards-with 'CHIP[[:space:]:=]*it83xx')" [lm4]="$(boards-with 'CHIP[[:space:]:=]*lm4')" - [mec1322]="$(boards-with 'CHIP[[:space:]:=]*mec1322')" [max32660]="$(boards-with 'CHIP[[:space:]:=]*max32660')" [mt_scp]="$(boards-with 'CHIP[[:space:]:=]*mt_scp')" ) diff --git a/util/flash_ec b/util/flash_ec index 8419c2e7a0..6b89edd8fa 100755 --- a/util/flash_ec +++ b/util/flash_ec @@ -1612,10 +1612,6 @@ function flash_npcx_int_spi() { flash_flashrom } -function flash_mec1322() { - flash_flashrom -} - info "Using ${SERVO_TYPE}." # Only if it is a flash program request, call ec_image. |