diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2016-03-07 13:25:00 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-03-08 13:56:38 -0800 |
| commit | 541de8a5a37ad35aa6eb7b4d641ef7df377f90e0 (patch) | |
| tree | 5ad1a09c281e89e990eac60cce8ecc7757d12d1d | |
| parent | 9f39ce1903b7b7ab28c3cba582bf12d93f525394 (diff) | |
| download | chrome-ec-541de8a5a37ad35aa6eb7b4d641ef7df377f90e0.tar.gz | |
npcx: Rename CONFIG_SHI to CONFIG_HOSTCMD_SPS
CONFIG_SHI ("SPI host interface") has identical meaning to
CONFIG_HOSTCMD_SPS ("Accept EC host commands over the SPI slave"). Use
CONFIG_HOSTCMD_SPS, since it came first and is already defined in config.h.
BUG=chrome-os-partner:50819
BRANCH=None
TEST=`make buildall -j`
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I665c405ad72caa3b84e583a80c0893e4c625632a
Reviewed-on: https://chromium-review.googlesource.com/331342
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
| -rw-r--r-- | board/npcx_evb_arm/board.h | 2 | ||||
| -rw-r--r-- | chip/npcx/build.mk | 2 | ||||
| -rw-r--r-- | chip/npcx/gpio.c | 2 | ||||
| -rw-r--r-- | chip/npcx/shi_chip.h | 4 |
4 files changed, 5 insertions, 5 deletions
diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h index 4678d86224..ca572b8a0b 100644 --- a/board/npcx_evb_arm/board.h +++ b/board/npcx_evb_arm/board.h @@ -11,7 +11,7 @@ /* Optional modules */ #define CONFIG_ADC #define CONFIG_PWM -#define CONFIG_SHI /* Used in ARM-based platform for host interface */ +#define CONFIG_HOSTCMD_SPS /* Used in ARM-based platform for host interface */ /* Optional features */ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */ diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index 09f59e3710..8240634be6 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -21,7 +21,7 @@ chip-$(CONFIG_FLASH)+=flash.o chip-$(CONFIG_I2C)+=i2c.o chip-$(CONFIG_LPC)+=lpc.o chip-$(CONFIG_PECI)+=peci.o -chip-$(CONFIG_SHI)+=shi.o +chip-$(CONFIG_HOSTCMD_SPS)+=shi.o # pwm functions are implemented with the fan functions chip-$(CONFIG_PWM)+=pwm.o chip-$(CONFIG_SPI)+=spi.o diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index bd310b214f..9dae6d0f6f 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -679,7 +679,7 @@ void gpio_pre_init(void) #endif /* Pin_Mux for LPC & SHI */ -#ifdef CONFIG_SHI +#ifdef CONFIG_HOSTCMD_SPS /* Switching to eSPI mode for SHI interface */ NPCX_DEVCNT |= 0x08; /* Alternate Intel bus interface LPC/eSPI to GPIOs first */ diff --git a/chip/npcx/shi_chip.h b/chip/npcx/shi_chip.h index 2edd513bfc..8aac7661a5 100644 --- a/chip/npcx/shi_chip.h +++ b/chip/npcx/shi_chip.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,7 +8,7 @@ #ifndef SHI_CHIP_H_ #define SHI_CHIP_H_ -#ifdef CONFIG_SHI +#ifdef CONFIG_HOSTCMD_SPS /** * Called when the NSS level changes, signalling the start of a SHI * transaction. |