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author | johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com> | 2022-07-11 10:26:01 +0800 |
---|---|---|
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-07-19 04:01:03 +0000 |
commit | 2911d8fd06d986916a0b7a2329c473c54ae5297d (patch) | |
tree | 0a27603b609b1840849b8c70e04486ac1b914aab | |
parent | e8c32a46aff3cc81751979ff46df4bfb3277f53b (diff) | |
download | chrome-ec-2911d8fd06d986916a0b7a2329c473c54ae5297d.tar.gz |
Banshee: Config BBR USB3 bit for USB card port in suspend/resume
For some chromebooks design, there are expansion card (typeC to typeA)
communicate with TCPC through CC line, when the TypeA card connect to
chromebook the USB3_Connection bit would be enable even no connect USBA
device.
It will increase BBR power consumption, so clear 'USB3_Connection' bit
in S0ix and enable when return S0.
Suspend -> Set BBR USB3 connection bit to 0 for port that is in USB3
connection.
Resume -> Unplug any type-c device in suspend will wake up the system
in current Chrome OS, so enable USB3_Connection bit should be perfromed
for another resume case which is USB3 device still in connection.
BUG=b:233975818
BRANCH=None
TEST=Test on Banshee, BBR USB3 connection bit is correct in S0/S0ix state.
Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com>
Change-Id: Ie6cb5d64578663a8e93378e3c78359e7cdd19327
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3754781
Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
-rw-r--r-- | board/banshee/board.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/board/banshee/board.c b/board/banshee/board.c index c751400d79..0814f35a9b 100644 --- a/board/banshee/board.c +++ b/board/banshee/board.c @@ -16,6 +16,7 @@ #include "hooks.h" #include "driver/als_tcs3400.h" #include "driver/charger/isl9241.h" +#include "driver/retimer/bb_retimer.h" #include "fw_config.h" #include "hooks.h" #include "keyboard_customization.h" @@ -33,15 +34,38 @@ #define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) #define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) +/* + * USBA card connect to chromebook the USB_3_CONNECTION + * bit would be enable. + * It will increase BBR power consumption, so clear + * USB3_Connection bit in S0ix and enable when return S0. + */ +void set_bb_retimer_usb3_state(bool enable) +{ + mux_state_t mux_state = 0; + + for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + const struct usb_mux *mux = &usb_muxes[i]; + + mux_state = usb_mux_get(i); + + if ((mux_state & USB_PD_MUX_USB_ENABLED)) { + bb_retimer_set_usb3(mux, enable); + } + } +} + /* Called on AP S3 -> S0 transition */ static void board_chipset_resume(void) { + set_bb_retimer_usb3_state(true); } DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); /* Called on AP S0 -> S3 transition */ static void board_chipset_suspend(void) { + set_bb_retimer_usb3_state(false); } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); |