diff options
| author | li feng <li1.feng@intel.com> | 2015-11-13 10:55:37 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-11-18 17:03:56 -0800 |
| commit | 93760af711a283eb165158c4b9063465b96cb3ca (patch) | |
| tree | a96a5a6ba96e86db6667604ae6896f1a4b1db3ef | |
| parent | 420099f74976b3af1f4b24dc24b9fec461b1037b (diff) | |
| download | chrome-ec-93760af711a283eb165158c4b9063465b96cb3ca.tar.gz | |
mec1322: i2c: clear specified status bits
In handle_interrupt(), "|= 1 << 29" will clears all status bits, not
just bit 29. Fix this to make it only clear specified status bit and
keep R/W bits intact.
BUG=None
BRANCH=None
TEST=Verified on Kunimitus system
1. In configure_controller() write R/W bits in completion register
2. In handle_interrupt() print the value of completion register and
status bits is cleared, R/W bits are kept.
Change-Id: I6a9cc17b3dfc1e163af5e56a80600afb8ac23247
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/312701
Commit-Ready: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | chip/mec1322/i2c.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c index 61f6af7918..8cf92cb860 100644 --- a/chip/mec1322/i2c.c +++ b/chip/mec1322/i2c.c @@ -35,6 +35,10 @@ #define CTRL_ESO (1 << 6) /* Enable serial output */ #define CTRL_PIN (1 << 7) /* Pending interrupt not */ +/* Completion */ +#define COMP_IDLE (1 << 29) /* i2c bus is idle */ +#define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */ + /* Maximum transfer of a SMBUS block transfer */ #define SMBUS_MAX_BLOCK_SIZE 32 @@ -457,7 +461,7 @@ static void handle_interrupt(int controller) int id = cdata[controller].task_waiting; /* Clear the interrupt status */ - MEC1322_I2C_COMPLETE(controller) |= 1 << 29; + MEC1322_I2C_COMPLETE(controller) &= (COMP_RW_BITS_MASK | COMP_IDLE); /* * Write to control register interferes with I2C transaction. |