it8380dev: improve power consumption

In doze mode, these improvements help reduce EC power consumption.

Signed-off-by: Dino Li <dino.li@ite.com.tw>

BRANCH=none
BUG=none
TEST=Power consumption has reduced.

Change-Id: I8b0fe3301e408134284b4ac5778656ba9b92b0f1
Reviewed-on: https://chromium-review.googlesource.com/312632
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

6 files changed, 54 insertions, 6 deletions

diff --git a/board/it8380dev/board.c b/board/it8380dev/board.c
index 0a746761c5..61ffbacf05 100644
--- a/board/it8380dev/board.c
+++ b/board/it8380dev/board.c
@@ -6,6 +6,7 @@
 
 #include "adc.h"
 #include "adc_chip.h"
+#include "clock.h"
 #include "common.h"
 #include "console.h"
 #include "ec2i_chip.h"
@@ -180,6 +181,23 @@ static void board_init(void)
 	 * use console command "sleepmask" to enable it if necessary.
 	 */
 	disable_sleep(SLEEP_MASK_FORCE_NO_DSLEEP);
+	/*
+	 * The GPIOH.5/6 may be used for flashing purposes if WP pin
+	 * is deasserted. The clock of this module needs to be enabled.
+	 * So we disable the clock when WP pin is asserted,
+	 * this can help to reduce power consumption.
+	 */
+#ifdef CONFIG_WP_ACTIVE_HIGH
+	if (gpio_get_level(GPIO_WP))
+		clock_disable_peripheral(CGC_OFFSET_USB, 0, 0);
+	else
+		clock_enable_peripheral(CGC_OFFSET_USB, 0, 0);
+#else
+	if (!gpio_get_level(GPIO_WP_L))
+		clock_disable_peripheral(CGC_OFFSET_USB, 0, 0);
+	else
+		clock_enable_peripheral(CGC_OFFSET_USB, 0, 0);
+#endif
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
index 7775ca3d64..a957782815 100644
--- a/chip/it83xx/clock.c
+++ b/chip/it83xx/clock.c
@@ -51,6 +51,19 @@ struct clock_gate_ctrl {
 	uint8_t mask;
 };
 
+static void clock_module_disable(void)
+{
+	/* bit0: FSPI interface tri-state */
+	IT83XX_SMFI_FLHCTRL3R |= (1 << 0);
+	/* bit7: USB pad power-on disable */
+	IT83XX_GCTRL_PMER2 &= ~(1 << 7);
+	clock_disable_peripheral((CGC_OFFSET_EGPC | CGC_OFFSET_CIR), 0, 0);
+	clock_disable_peripheral((CGC_OFFSET_SMBA | CGC_OFFSET_SMBB |
+		CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | CGC_OFFSET_SMBE |
+		CGC_OFFSET_SMBF), 0, 0);
+	clock_disable_peripheral((CGC_OFFSET_SSPI | CGC_OFFSET_PECI), 0, 0);
+}
+
 void clock_init(void)
 {
 #if PLL_CLOCK == 48000000
@@ -80,6 +93,8 @@ void clock_init(void)
 	/* Default doze mode */
 	IT83XX_ECPM_PLLCTRL = EC_PLL_DOZE;
 
+	clock_module_disable();
+
 #if defined(CONFIG_LPC) && defined(CONFIG_IT83XX_LPC_ACCESS_INT)
 	IT83XX_WUC_WUESR4 = 0xff;
 	task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c
index d9e8bbde0a..d2aac92604 100644
--- a/chip/it83xx/i2c.c
+++ b/chip/it83xx/i2c.c
@@ -107,12 +107,13 @@ static const struct i2c_pin i2c_pin_regs[] = {
 
 struct i2c_ctrl_t {
 	uint8_t irq;
+	enum clock_gate_offsets clock_gate;
 };
 
 const struct i2c_ctrl_t i2c_ctrl_regs[] = {
-	{IT83XX_IRQ_SMB_A},
-	{IT83XX_IRQ_SMB_B},
-	{IT83XX_IRQ_SMB_C},
+	{IT83XX_IRQ_SMB_A, CGC_OFFSET_SMBA},
+	{IT83XX_IRQ_SMB_B, CGC_OFFSET_SMBB},
+	{IT83XX_IRQ_SMB_C, CGC_OFFSET_SMBC},
 };
 
 enum i2c_ch_status {
@@ -511,6 +512,7 @@ static void i2c_init(void)
 	for (i = 0; i < i2c_ports_used; i++) {
 		/* I2c port mapping. */
 		p = i2c_ports[i].port;
+		clock_enable_peripheral(i2c_ctrl_regs[p].clock_gate, 0, 0);
 		/*
 		 * bit0, The SMBus host interface is enabled.
 		 * bit1, Enable to communicate with I2C device and
diff --git a/chip/it83xx/peci.c b/chip/it83xx/peci.c
index 1f167b3f43..7aa1dbb0e8 100644
--- a/chip/it83xx/peci.c
+++ b/chip/it83xx/peci.c
@@ -124,6 +124,9 @@ static enum peci_status peci_transaction(uint8_t addr,
 	uint8_t status;
 	int index;
 
+	/* To enable PECI function pin */
+	IT83XX_GPIO_GPCRF6 = 0x00;
+
 	/*
 	 * bit5, Both write and read data FIFO pointers will be cleared.
 	 *
@@ -239,6 +242,9 @@ static enum peci_status peci_transaction(uint8_t addr,
 	/* W/C */
 	IT83XX_PECI_HOSTAR = PECI_STATUS_ANY_BIT;
 
+	/* Disable PECI function pin */
+	IT83XX_GPIO_GPCRF6 = 0x80;
+
 	return status;
 }
 
@@ -321,14 +327,12 @@ static void peci_init(void)
 {
 	int i;
 
+	clock_enable_peripheral(CGC_OFFSET_PECI, 0, 0);
 	peci_init_vtt_freq();
 
 	/* bit3,this bit enables the PECI host controller. */
 	IT83XX_PECI_HOCTLR |= 0x08;
 
-	/* To enable PECI function pin */
-	IT83XX_GPIO_GPCRF6 = 0x00;
-
 	/* bit4, PECI enable */
 	IT83XX_GPIO_GRC2 |= 0x10;
 
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index 09949b0615..1d0f79c31d 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -609,6 +609,12 @@ enum clock_gate_offsets {
 	CGC_OFFSET_UART  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x04),
 	CGC_OFFSET_SSPI  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x02),
 	CGC_OFFSET_DBGR  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x01),
+	CGC_OFFSET_SMBF  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x80),
+	CGC_OFFSET_SMBE  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x40),
+	CGC_OFFSET_SMBD  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x20),
+	CGC_OFFSET_SMBC  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x10),
+	CGC_OFFSET_SMBB  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08),
+	CGC_OFFSET_SMBA  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04),
 	CGC_OFFSET_SMB   = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x02),
 	CGC_OFFSET_CEC   = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x01)
 };
@@ -659,6 +665,7 @@ enum clock_gate_offsets {
 #define IT83XX_GCTRL_RSTC4        REG8(IT83XX_GCTRL_BASE+0x11)
 #define IT83XX_GCTRL_SPCTRL4      REG8(IT83XX_GCTRL_BASE+0x1C)
 #define IT83XX_GCTRL_MCCR         REG8(IT83XX_GCTRL_BASE+0x30)
+#define IT83XX_GCTRL_PMER2        REG8(IT83XX_GCTRL_BASE+0x33)
 #define IT83XX_GCTRL_EPLR         REG8(IT83XX_GCTRL_BASE+0x37)
 #define IT83XX_GCTRL_IVTBAR       REG8(IT83XX_GCTRL_BASE+0x41)
 #define IT83XX_GCTRL_MCCR2        REG8(IT83XX_GCTRL_BASE+0x44)
@@ -899,6 +906,7 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4))
 #define IT83XX_SMFI_SCAR2L      REG8(IT83XX_SMFI_BASE+0x46)
 #define IT83XX_SMFI_SCAR2M      REG8(IT83XX_SMFI_BASE+0x47)
 #define IT83XX_SMFI_SCAR2H      REG8(IT83XX_SMFI_BASE+0x48)
+#define IT83XX_SMFI_FLHCTRL3R   REG8(IT83XX_SMFI_BASE+0x63)
 #define IT83XX_SMFI_STCDMACR    REG8(IT83XX_SMFI_BASE+0x80)
 
 /* Serial Peripheral Interface (SSPI) */
diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c
index df7158b701..e02c3d590d 100644
--- a/chip/it83xx/spi.c
+++ b/chip/it83xx/spi.c
@@ -146,6 +146,7 @@ static void sspi_init(void)
 {
 	int i;
 
+	clock_enable_peripheral(CGC_OFFSET_SSPI, 0, 0);
 	sspi_frequency(sspi_clk_8mhz);
 
 	/*