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| author | Mulin Chao <mlchao@nuvoton.com> | 2016-01-06 11:40:07 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-01-06 20:43:40 -0800 |
| commit | a48945568e22c28e67b64453252ad4e9387d0e06 (patch) | |
| tree | e00a4141a8d3b15dced697cd23d8431f7c8e0b1a | |
| parent | a4175c650eaeb66a7537d25358744b5a36292416 (diff) | |
| download | chrome-ec-a48945568e22c28e67b64453252ad4e9387d0e06.tar.gz | |
wheatley: Proposed workaround for RESET_FLAG_RESET_PIN issue on wheatley.
During pressing VolUp + VolDn + Pwr buttons, Silego polls down both EC_RST_L
and ROP_LDO_EN on wheatley. Beside VCC1_RST occurs, power-on reset also occurs
simultaneously since EC's power rail is turned off by PMIC for a while.
VCC1_RST_STS bit is cleared by power-on reset and it will influence recovery
mode detection.
The workaround treats no matter power-on or VCC1_RST reset as reset-pin reset.
Use BOARD_WHEATLEY to distinguish them.
Modified drivers:
1. system.c: Proposed workaround for RESET_FLAG_RESET_PIN issue.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I96198ffb6901f0539755046ca303e94381ae7541
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320641
Reviewed-by: Randall Spangler <rspangler@chromium.org>
| -rw-r--r-- | chip/npcx/system.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/chip/npcx/system.c b/chip/npcx/system.c index a5b51c6609..544e88e05d 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -157,11 +157,15 @@ void system_check_reset_cause(void) /* Use scratch bit to check power on reset or VCC1_RST reset */ if (!IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH)) { +#ifdef BOARD_WHEATLEY + flags |= RESET_FLAG_RESET_PIN; +#else /* Check for VCC1 reset */ if (IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS)) flags |= RESET_FLAG_RESET_PIN; else flags |= RESET_FLAG_POWER_ON; +#endif } /* |