cr50: generate HARD RESET when sys_reset is asserted

This patch replaces a long standing stub. When the EC asserts this
signal, the CR50 must reset.

But this signal could be driven by CR50 itself as well, and in that
case the signal's assertion should not be causing the CR50 reset.

Ideally it should be possible to tell if the pin is configured as
output and ignore its assertion in that case. But there is no API for
checking the pin configuration settings at this time. An API function
is added to check if the AP Flash is being programmed, the GPIO
configuration access API is left for future enhancements.

BRANCH=none
BUG=chrome-os-partner:52366, chrome-os-partner:54982
TEST=issue 'reboot' command from the bash command line.
   - verify on the cr50 console that it reboots along with the rest of
     the device
   - observe that reading of the NVRam spaces is still fully
     functional, and Kevin can boot all the way up to the login
     screen.
   - try flashing AP firmware through CR50, verify that it succeed.

Change-Id: Ie4506238dc8b158b32121719a2db7fd232fd7d6c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357967
Reviewed-by: Shawn N <shawnn@chromium.org>

3 files changed, 27 insertions, 2 deletions

diff --git a/board/cr50/board.c b/board/cr50/board.c
index 3910af7159..e7995f08a8 100644
--- a/board/cr50/board.c
+++ b/board/cr50/board.c
@@ -14,6 +14,7 @@
 #include "init_chip.h"
 #include "registers.h"
 #include "nvmem.h"
+#include "system.h"
 #include "task.h"
 #include "trng.h"
 #include "uartn.h"
@@ -21,6 +22,7 @@
 #include "usb_hid.h"
 #include "util.h"
 #include "spi.h"
+#include "usb_spi.h"
 
 /* Define interrupt and gpio structs */
 #include "gpio_list.h"
@@ -205,8 +207,16 @@ int flash_regions_to_enable(struct g_flash_region *regions,
 
 void sys_rst_asserted(enum gpio_signal signal)
 {
-	/* TODO(crosbug.com/p/52366): Do something useful here. */
-	CPRINTS("%s(%d)", __func__, signal);
+	/*
+	 * Cr50 drives SYS_RST_L in certain scenarios, in those cases
+	 * asserting this signal should not cause a system reset.
+	 */
+	CPRINTS("%s resceived signal %d)", __func__, signal);
+	if (ap_spi_update_in_progress())
+		return;
+
+	cflush();
+	system_reset(SYSTEM_RESET_HARD);
 }
 
 void nvmem_compute_sha(uint8_t *p_buf, int num_bytes,
diff --git a/board/cr50/usb_spi.c b/board/cr50/usb_spi.c
index 53ad5702be..441ae94ae6 100644
--- a/board/cr50/usb_spi.c
+++ b/board/cr50/usb_spi.c
@@ -12,6 +12,8 @@
 
 #define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
 
+static uint8_t sys_rst_l_state = 1;
+
 void disable_spi(void)
 {
 	/* Configure SPI GPIOs */
@@ -20,6 +22,7 @@ void disable_spi(void)
 
 	/* Release AP and EC */
 	GWRITE(RBOX, ASSERT_EC_RST, 0);
+	sys_rst_l_state = 1;
 	gpio_set_level(GPIO_SYS_RST_L_OUT, 1);
 
 	/* Set SYS_RST_L as an input otherwise cr50 will hold the AP in reset */
@@ -48,9 +51,15 @@ void enable_ap_spi(void)
 	gpio_set_flags(GPIO_SYS_RST_L_OUT, GPIO_OUT_HIGH);
 
 	/* hold EC in reset */
+	sys_rst_l_state = 0;
 	gpio_set_level(GPIO_SYS_RST_L_OUT, 0);
 }
 
+int ap_spi_update_in_progress(void)
+{
+	return !sys_rst_l_state;
+}
+
 void usb_spi_board_enable(struct usb_spi_config const *config)
 {
 	disable_spi();
diff --git a/chip/g/usb_spi.h b/chip/g/usb_spi.h
index 67d9b3230c..2002d93e9f 100644
--- a/chip/g/usb_spi.h
+++ b/chip/g/usb_spi.h
@@ -227,4 +227,10 @@ int usb_spi_interface(struct usb_spi_config const *config,
 void usb_spi_board_enable(struct usb_spi_config const *config);
 void usb_spi_board_disable(struct usb_spi_config const *config);
 
+/*
+ * Returns true if AP SPI update is running, needed to properly handle
+ * SYS_RST_L input state changes.
+ */
+int ap_spi_update_in_progress(void);
+
 #endif /* __CROS_EC_USB_SPI_H */