diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2017-11-08 12:56:40 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-11-14 10:11:19 -0800 |
| commit | 68bd2d4fb278781d1ff7c40f42f43e8e445d89ac (patch) | |
| tree | ba868a4334eacce39c60a1f1a098fe3bbf9b6195 | |
| parent | b6991dd96d8bf6cb86a39b3da590ccd8b4e1e036 (diff) | |
| download | chrome-ec-68bd2d4fb278781d1ff7c40f42f43e8e445d89ac.tar.gz | |
npcx: Use compatible MPU config
MPU is already configured for access restriction in cortex-m core code
so take care not to conflict.
BUG=chromium:782244
BRANCH=None
TEST=Build + boot on kevin, verify hibernate doesn't panic.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9903cbc69002529ebbfa3fc1be3de4f74264e4aa
Reviewed-on: https://chromium-review.googlesource.com/759157
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
| -rw-r--r-- | chip/npcx/system-npcx5.c | 32 | ||||
| -rw-r--r-- | chip/npcx/system-npcx7.c | 23 |
2 files changed, 7 insertions, 48 deletions
diff --git a/chip/npcx/system-npcx5.c b/chip/npcx/system-npcx5.c index abbc8b1e45..b991bb18b8 100644 --- a/chip/npcx/system-npcx5.c +++ b/chip/npcx/system-npcx5.c @@ -7,14 +7,15 @@ #include "common.h" #include "console.h" #include "cpu.h" +#include "gpio.h" +#include "hwtimer_chip.h" +#include "mpu.h" #include "registers.h" +#include "rom_chip.h" #include "system.h" +#include "system_chip.h" #include "task.h" #include "util.h" -#include "gpio.h" -#include "hwtimer_chip.h" -#include "system_chip.h" -#include "rom_chip.h" /* Begin address of Suspend RAM for hibernate utility */ uintptr_t __lpram_fw_start = CONFIG_LPRAM_BASE; @@ -35,8 +36,8 @@ void system_mpu_config(void) /* Enable MPU */ CPU_MPU_CTRL = 0x7; - /* Create a new MPU Region for low-power ram */ - CPU_MPU_RNR = 0; /* Select region number 0 */ + /* Create a new MPU Region to allow execution from low-power ram */ + CPU_MPU_RNR = REGION_CHIP_RESERVED; CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */ CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */ /* @@ -53,25 +54,6 @@ void system_mpu_config(void) * [0] - ENABLE = 1 (enabled) */ CPU_MPU_RASR = 0x03080013; - - /* Create a new MPU Region for data ram */ - CPU_MPU_RNR = 1; /* Select region number 1 */ - CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */ - CPU_MPU_RBAR = CONFIG_RAM_BASE; /* Set region base address */ - /* - * Set region size & attribute and enable region - * [31:29] - Reserved. - * [28] - XN (Execute Never) = 1 - * [27] - Reserved. - * [26:24] - AP = 011 (Full access) - * [23:22] - Reserved. - * [21:19,18,17,16] - TEX,S,C,B = 001000 (Normal memory) - * [15:8] - SRD = 0 (Subregions enabled) - * [7:6] - Reserved. - * [5:1] - SIZE = 01110 (32K) - * [0] - ENABLE = 1 (enabled) - */ - CPU_MPU_RASR = 0x1308001D; } /** diff --git a/chip/npcx/system-npcx7.c b/chip/npcx/system-npcx7.c index e22a5cece0..c476945e42 100644 --- a/chip/npcx/system-npcx7.c +++ b/chip/npcx/system-npcx7.c @@ -25,29 +25,6 @@ void system_mpu_config(void) { - /* Enable MPU */ - CPU_MPU_CTRL = 0x7; - - /* Create a new MPU Region for data ram */ - CPU_MPU_RNR = 0; /* Select region number 0 */ - CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */ - CPU_MPU_RBAR = CONFIG_RAM_BASE; /* Set region base address */ - /* - * Set region size & attribute and enable region - * [31:29] - Reserved. - * [28] - XN (Execute Never) = 1 - * [27] - Reserved. - * [26:24] - AP = 011 (Full access) - * [23:22] - Reserved. - * [21:19,18,17,16] - TEX,S,C,B = 001000 (Normal memory) - * [15:8] - SRD = 0 (Subregions enabled) - * [7:6] - Reserved. - * [5:1] - SIZE = 01111 (64KB in NPCX796F) - * [0] - ENABLE = 1 (enabled) - */ - /* TODO: Add the configurations for the other npcx7 series. */ - CPU_MPU_RASR = 0x1308001F; - } #ifdef CONFIG_HIBERNATE_PSL |