diff options
| author | Divya Jyothi <divya.jyothi@intel.com> | 2016-03-04 13:47:48 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-03-17 16:42:36 -0700 |
| commit | e3623405c62d7216dff5d85a190f3012fb9fc6dc (patch) | |
| tree | 644c7fc70abc9959d24d0ffd4c510584b5cc57d1 | |
| parent | d3a8bd0c36bea7c33caecb72058b769170471fd1 (diff) | |
| download | chrome-ec-e3623405c62d7216dff5d85a190f3012fb9fc6dc.tar.gz | |
mec1322: Do not shutdown LPC in deepsleep.
During the resume sequence of S0ix EC can receive host commands early
in the resume path when LPC is still disabled in EC. Host messages
will be lost if the LPC interface with the kernel is down.
Clock control was programed to 2 which means ring oscillator is
shut down after completion of everty LPC transaction.To restart
the oscillator EC should enable a wake interrupt on LPC LFRAME number
and this mode can cause an increase in the time to
respond to the LPC transactions.
Keeping LPC always on shows minimal power impact as per datasheet
Pg.390. The impact is < 0.45mW.
BUG=chrome-os-partner:50627
TEST=Enter into S0ix and exit reliably.
BRANCH=firmware-glados-7820.B
Change-Id: I670b9b45c3a85c9bca249312a73a25dca52b313a
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/332333
Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit c03fd6e0eaa6ecd3205214f901facb9896a798b4)
Reviewed-on: https://chromium-review.googlesource.com/332791
| -rw-r--r-- | chip/mec1322/clock.c | 7 | ||||
| -rw-r--r-- | chip/mec1322/lpc.c | 8 |
2 files changed, 10 insertions, 5 deletions
diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c index ba46e4e1a2..8a5fb73047 100644 --- a/chip/mec1322/clock.c +++ b/chip/mec1322/clock.c @@ -201,9 +201,9 @@ static void prepare_for_deep_sleep(void) MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP; MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP; +#ifndef CONFIG_POWER_S0IX MEC1322_LPC_ACT = 0x0; - MEC1322_LPC_CLK_CTRL |= 0x2; - +#endif MEC1322_PCR_SLOW_CLK_CTL &= 0xFFFFFC00; MEC1322_PCR_SYS_SLP_CTL = 0x2; /* heavysleep 2 */ @@ -236,9 +236,10 @@ static void resume_from_deep_sleep(void) MEC1322_PCR_SYS_SLP_CTL = 0xF8; /* default */ +#ifndef CONFIG_POWER_S0IX /* Enable LPC */ MEC1322_LPC_ACT |= 1; - MEC1322_LPC_CLK_CTRL &= ~0x2; +#endif MEC1322_PCR_SLOW_CLK_CTL = 0x1E0; } diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index e58d7138ff..c97b74760c 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -315,6 +315,12 @@ static void lpc_init(void) /* Activate LPC interface */ MEC1322_LPC_ACT |= 1; + /* + * Ring Oscillator not permitted to shut down + * until LPC activate bit is cleared + */ + MEC1322_LPC_CLK_CTRL |= 3; + /* Initialize host args and memory map to all zero */ memset(lpc_host_args, 0, sizeof(*lpc_host_args)); memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE); @@ -323,8 +329,6 @@ static void lpc_init(void) /* Restore event masks if needed */ lpc_post_sysjump(); - - } /* * Set prio to higher than default; this way LPC memory mapped data is ready |