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| author | Randall Spangler <rspangler@chromium.org> | 2013-05-20 12:53:55 -0700 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-05-23 11:08:43 -0700 |
| commit | aa419b29ac9d012333a416696c7449047e085d29 (patch) | |
| tree | 8cc437517d76723839a641e6dd1faa995cae9f59 | |
| parent | e8ecda5e8d0384ddc8fe6b3bd9e991ee6d84faae (diff) | |
| download | chrome-ec-aa419b29ac9d012333a416696c7449047e085d29.tar.gz | |
Clean up option byte register definitions for STM32L
No functional changes, just renaming and defining a few additional regs.
BUG=chrome-os-partner:15613
BRANCH=none
TEST=build pit
Change-Id: I67b2a96608431ffc418e6d4c81009d497f34568b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/55813
| -rw-r--r-- | chip/stm32/flash-stm32l15x.c | 8 | ||||
| -rw-r--r-- | chip/stm32/registers.h | 18 |
2 files changed, 13 insertions, 13 deletions
diff --git a/chip/stm32/flash-stm32l15x.c b/chip/stm32/flash-stm32l15x.c index d110267fa6..8fa1d711d4 100644 --- a/chip/stm32/flash-stm32l15x.c +++ b/chip/stm32/flash-stm32l15x.c @@ -140,8 +140,8 @@ static void write_optb(int offset, uint16_t value) */ static uint32_t read_optb_wrp(void) { - return read_optb(STM32_OPTB_WRP01) | - ((uint32_t)read_optb(STM32_OPTB_WRP23) << 16); + return read_optb(STM32_OPTB_WRP1L) | + ((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16); } /** @@ -149,8 +149,8 @@ static uint32_t read_optb_wrp(void) */ static void write_optb_wrp(uint32_t value) { - write_optb(STM32_OPTB_WRP01, (uint16_t)value); - write_optb(STM32_OPTB_WRP23, value >> 16); + write_optb(STM32_OPTB_WRP1L, (uint16_t)value); + write_optb(STM32_OPTB_WRP1H, value >> 16); } /** diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 148d1f2e08..adc1ed1b70 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -496,15 +496,15 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) #define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) -#define STM32_OPTB_BASE 0x1FF80000 - -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x04 -#define STM32_OPTB_WRP01 0x08 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&1) + (n&2) * 2) -#define STM32_OPTB_WRP23 0x0c - -#define STM32_OPTB_COMPL_SHIFT 16 +#define STM32_OPTB_BASE 0x1ff80000 +#define STM32_OPTB_RDP 0x00 +#define STM32_OPTB_USER 0x04 +#define STM32_OPTB_WRP1L 0x08 +#define STM32_OPTB_WRP1H 0x0c +#define STM32_OPTB_WRP2L 0x10 +#define STM32_OPTB_WRP2H 0x14 +#define STM32_OPTB_WRP3L 0x18 +#define STM32_OPTB_WRP3H 0x1c #elif defined(CHIP_VARIANT_stm32f100) || defined(CHIP_VARIANT_stm32f10x) #define STM32_FLASH_REGS_BASE 0x40022000 |