diff options
| author | ChromeOS Developer <rspangler@chromium.org> | 2013-07-03 11:43:29 -0700 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-07-08 13:53:58 -0700 |
| commit | 4e31062449cce3a86cd855403c147213cdbd06cc (patch) | |
| tree | 3ffd48879a5a4a4dfa090c9770a65ee6f4e7b197 | |
| parent | b013fd4e9cfb33c2b23e067d597a09830677e526 (diff) | |
| download | chrome-ec-4e31062449cce3a86cd855403c147213cdbd06cc.tar.gz | |
stm32: Clean up JTAG registers
No functional changes, just cleanup.
BUG=chrome-os-partner:20529
BRANCH=none
TEST=boot pit
Change-Id: I2067dffc3b1335f001a95e63b22213a1022f3ae8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61095
| -rw-r--r-- | chip/stm32/hwtimer.c | 10 | ||||
| -rw-r--r-- | chip/stm32/jtag-stm32l.c | 11 | ||||
| -rw-r--r-- | chip/stm32/registers.h | 15 |
3 files changed, 30 insertions, 6 deletions
diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c index 5957e0e974..6ac971f44d 100644 --- a/chip/stm32/hwtimer.c +++ b/chip/stm32/hwtimer.c @@ -165,21 +165,25 @@ void __hw_timer_enable_clock(int n, int enable) volatile uint32_t *reg; uint32_t mask = 0; + /* + * Mapping of timers to reg/mask is split into a few different ranges, + * some specific to individual chips. + */ #if defined(CHIP_FAMILY_stm32f) if (n == 1) { reg = &STM32_RCC_APB2ENR; - mask = 1 << 11; + mask = STM32_RCC_PB2_TIM1; } #elif defined(CHIP_FAMILY_stm32l) if (n >= 9 && n <= 11) { reg = &STM32_RCC_APB2ENR; - mask = 1 << (n - 7); + mask = STM32_RCC_PB2_TIM9 << (n - 9); } #endif if (n >= 2 && n <= 7) { reg = &STM32_RCC_APB1ENR; - mask = 1 << (n - 2); + mask = STM32_RCC_PB1_TIM2 << (n - 2); } if (!mask) diff --git a/chip/stm32/jtag-stm32l.c b/chip/stm32/jtag-stm32l.c index 71e5f711e2..f4ac4b0ae8 100644 --- a/chip/stm32/jtag-stm32l.c +++ b/chip/stm32/jtag-stm32l.c @@ -9,6 +9,13 @@ void jtag_pre_init(void) { - /* stop TIM2-4 and watchdogs when the JTAG stops the CPU */ - STM32_DBGMCU_APB1FZ |= 0x00001807; + /* + * Stop all timers we might use (TIM2-4,9-11) and watchdogs when + * the JTAG stops the CPU. + */ + STM32_DBGMCU_APB1FZ |= + STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + STM32_DBGMCU_APB2FZ |= STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 | + STM32_RCC_PB2_TIM11; } diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index fb84018ac5..48ebf1242b 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -347,6 +347,9 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x34) #define STM32_RCC_HB_DMA1 (1 << 24) +#define STM32_RCC_PB2_TIM9 (1 << 2) +#define STM32_RCC_PB2_TIM10 (1 << 3) +#define STM32_RCC_PB2_TIM11 (1 << 4) #define STM32_SYSCFG_BASE 0x40010000 @@ -370,12 +373,22 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) /* STM32F100 */ #define STM32_RCC_HB_DMA1 (1 << 0) +#define STM32_RCC_PB2_TIM1 (1 << 11) #else #error Unsupported chip variant #endif -/* Peripheral bits for RCC_APB/AHB regs */ +/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ +#define STM32_RCC_PB1_TIM2 (1 << 0) +#define STM32_RCC_PB1_TIM3 (1 << 1) +#define STM32_RCC_PB1_TIM4 (1 << 2) +#define STM32_RCC_PB1_TIM5 (1 << 3) +#define STM32_RCC_PB1_TIM6 (1 << 4) +#define STM32_RCC_PB1_TIM7 (1 << 5) +#define STM32_RCC_PB1_RTC (1 << 10) /* DBGMCU only */ +#define STM32_RCC_PB1_WWDG (1 << 11) +#define STM32_RCC_PB1_IWDG (1 << 12) /* DBGMCU only */ #define STM32_RCC_PB1_USART2 (1 << 17) #define STM32_RCC_PB1_USART3 (1 << 18) #define STM32_RCC_PB1_USART4 (1 << 19) |