diff options
| author | Jett Rink <jettrink@chromium.org> | 2018-11-12 15:43:22 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-11-16 05:02:05 -0800 |
| commit | b2f28faa3b7f4f9d37b76dd4d7dbb2b3d50db435 (patch) | |
| tree | 7dd377ce839e1d32ddb9acd682ce832e6be37d32 | |
| parent | 2d1ab813cba0e2aeb6bc5ce482abcf33340d8f67 (diff) | |
| download | chrome-ec-b2f28faa3b7f4f9d37b76dd4d7dbb2b3d50db435.tar.gz | |
phaser: update gpio based on next rev
The reset pin for ANX3447 was added. This pin used to be a 1.8V signal and
it now a 3.3V signal, so we need to take care to ensure that older
boards don't try to drive 3.3V into the SoC.
Other changes are just renames.
BRANCH=none
BUG=none
TEST=current phaser (ID=2) works
Change-Id: Ife0a1617f94e4f4a40d43b16328d5540ea35b3ff
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1334031
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
| -rw-r--r-- | board/phaser/board.c | 15 | ||||
| -rw-r--r-- | board/phaser/gpio.inc | 17 |
2 files changed, 21 insertions, 11 deletions
diff --git a/board/phaser/board.c b/board/phaser/board.c index ccfd92086e..7680421a7b 100644 --- a/board/phaser/board.c +++ b/board/phaser/board.c @@ -232,6 +232,18 @@ static void board_update_sensor_config_from_sku(void) } } +/* This method can be removed once version 3+ boards are the majority */ +static void board_update_gpio_from_board_id(uint32_t board_id) +{ + /* + * GPIO83 used to be USB_OTG which is unused on the SoC side, but is + * a 1.8V signal. + */ + if (board_id < 3) { + gpio_set_flags(GPIO_USB_C0_PD_RST, GPIO_ODR_LOW); + } +} + static void cbi_init(void) { uint32_t val; @@ -240,6 +252,9 @@ static void cbi_init(void) sku_id = val; ccprints("SKU: 0x%04x", sku_id); + if (cbi_get_board_version(&val) == EC_SUCCESS) + board_update_gpio_from_board_id(val); + board_update_sensor_config_from_sku(); } DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1); diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc index 7205d1bf9d..855b0baf82 100644 --- a/board/phaser/gpio.inc +++ b/board/phaser/gpio.inc @@ -118,6 +118,7 @@ GPIO(EN_USB_A0_5V, PIN(6, 7), GPIO_OUT_LOW) /* Enable A0 5V Charging */ GPIO(EN_USB_A1_5V, PIN(9, 6), GPIO_OUT_LOW) /* Enable A1 5V Charging */ GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0 1.5A Charging */ GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH) /* Enable A1 1.5A Charging */ +GPIO(USB_C0_PD_RST, PIN(8, 3), GPIO_OUT_LOW) /* C0 PD Reset */ GPIO(USB_C0_BC12_VBUS_ON, PIN(6, 3), GPIO_OUT_LOW) /* C0 BC1.2 Power */ GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT) /* C0 BC1.2 Detect */ GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT | /* C0 DP Hotplug Detect */ @@ -128,16 +129,6 @@ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ GPIO_SEL_1P8V) -/* Not implemented in hardware yet */ -UNIMPLEMENTED(USB_C0_PD_RST) - -/* - * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it - * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it - * high. - */ -GPIO(USB2_OTG_ID, PIN(8, 3), GPIO_ODR_LOW) /* OTG ID */ - /* LED */ GPIO(BAT_LED_RED_L, PIN(C, 3), GPIO_OUT_HIGH) /* LED_1_L */ GPIO(BAT_LED_GREEN_L, PIN(C, 4), GPIO_OUT_HIGH) /* LED_2_L */ @@ -153,8 +144,12 @@ GPIO(USB_C_OC, PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) GPIO(GPO66_NC, PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP) GPIO(GPOB6_NC, PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP) +/* Camera */ +GPIO(EC_GPIO_03, PIN(0, 3), GPIO_INPUT) /* TP only */ +GPIO(EC_INT_L, PIN(9, 4), GPIO_INPUT) /* EC_AP_INT_ODL - Unused GPIO_ODR_HIGH */ + /* Misc. */ -GPIO(CCD_MODE_ODL, PIN(E, 3), GPIO_INPUT) +GPIO(CCD_MODE_EC_L, PIN(E, 3), GPIO_INPUT) /* Keyboard pins */ ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_00-01 */ |