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authorAnton Staaf <robotboy@chromium.org>2014-11-10 11:23:21 -0800
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2014-11-11 21:46:10 +0000
commit74a98425efd53098ed430e6817261cf6386cce3a (patch)
tree9bcda9a90b396fb0b9e8b2d89261e993652ed7e0
parent0f4a2c333ca003f47159c5988a631185ecd87eaa (diff)
downloadchrome-ec-74a98425efd53098ed430e6817261cf6386cce3a.tar.gz
USB: Fix issue with USB RAM sizes
Previously the USB RAM size was off by a factor of two for chips that required 32-bit alignment of accesses, even though the underlying memory was 16-bits in size. This change adds an additional configuration for the access size (it still assumes that the underlying memory is 16-bits in size) and uses that to adjust the USB_RAM memory section in the linker scripts. This change also removes the default values for the USB RAM from stm32/config_chip.h because they mask issues when new chips are added. It is better for a new chip to fail to compile until these values are provided. Finally, this change introduces a common USB API header so that common code doesn't need to include the STM32 specific header. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Enable console on ryu_p2 and discovery-stm32f072 board Verify that it works on both Change-Id: Id118627f53e9e8ff1bd09fb51f1f9634ff495d19 Reviewed-on: https://chromium-review.googlesource.com/228833 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
-rw-r--r--chip/stm32/config-stm32f07x.h7
-rw-r--r--chip/stm32/config-stm32f373.h7
-rw-r--r--chip/stm32/config-stm32l100.h6
-rw-r--r--chip/stm32/config-stm32l15x.h6
-rw-r--r--chip/stm32/config-stm32ts60.h6
-rw-r--r--chip/stm32/config_chip.h6
-rw-r--r--common/usb_pd_policy.c2
-rw-r--r--core/cortex-m/ec.lds.S4
-rw-r--r--core/cortex-m0/ec.lds.S4
-rw-r--r--include/usb.h20
-rw-r--r--include/usb_api.h41
11 files changed, 79 insertions, 30 deletions
diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h
index fd1b46bc98..bae4e254be 100644
--- a/chip/stm32/config-stm32f07x.h
+++ b/chip/stm32/config-stm32f07x.h
@@ -41,5 +41,8 @@
#undef CONFIG_CONSOLE_HISTORY
#define CONFIG_CONSOLE_HISTORY 3
-/* STM32F0 has a larger USB RAM */
-#define CONFIG_USB_RAM_SIZE 1024
+/* USB packet ram config */
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 1024
+#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
+#define CONFIG_USB_RAM_ACCESS_SIZE 2
diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h
index 2553702877..32a9d0b5fa 100644
--- a/chip/stm32/config-stm32f373.h
+++ b/chip/stm32/config-stm32f373.h
@@ -37,5 +37,8 @@
/* Number of IRQ vectors on the NVIC */
#define CONFIG_IRQ_COUNT 81
-/* STM32F3 has a larger USB RAM */
-#define CONFIG_USB_RAM_SIZE 512
+/* STM32F3 uses the older 4 byte aligned access mechanism */
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 512
+#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
+#define CONFIG_USB_RAM_ACCESS_SIZE 4
diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h
index 1d18b6c5e8..983f956b84 100644
--- a/chip/stm32/config-stm32l100.h
+++ b/chip/stm32/config-stm32l100.h
@@ -54,3 +54,9 @@
/* Fake hibernate mode */
#define CONFIG_STM32L_FAKE_HIBERNATE
+
+/* USB packet ram config */
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 512
+#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
+#define CONFIG_USB_RAM_ACCESS_SIZE 4
diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h
index 6e9b862dab..4ba9fe24b5 100644
--- a/chip/stm32/config-stm32l15x.h
+++ b/chip/stm32/config-stm32l15x.h
@@ -55,3 +55,9 @@
/* Flash erases to 0, not 1 */
#define CONFIG_FLASH_ERASED_VALUE32 0
+
+/* USB packet ram config */
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 512
+#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
+#define CONFIG_USB_RAM_ACCESS_SIZE 4
diff --git a/chip/stm32/config-stm32ts60.h b/chip/stm32/config-stm32ts60.h
index 2e92016830..0713b201d6 100644
--- a/chip/stm32/config-stm32ts60.h
+++ b/chip/stm32/config-stm32ts60.h
@@ -44,3 +44,9 @@
/* Only USART2 support */
#undef CONFIG_UART_CONSOLE
#define CONFIG_UART_CONSOLE 2
+
+/* USB packet ram config */
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 512
+#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
+#define CONFIG_USB_RAM_ACCESS_SIZE 4
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index ebd2f00acc..081e8ca478 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -88,10 +88,4 @@
/* Compile for running from RAM instead of flash */
/* #define COMPILE_FOR_RAM */
-/* Dedicated SRAM region for USB transfers */
-#define CONFIG_USB_RAM_BASE 0x40006000
-#ifndef CONFIG_USB_RAM_SIZE
-#define CONFIG_USB_RAM_SIZE 512
-#endif
-
#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/common/usb_pd_policy.c b/common/usb_pd_policy.c
index 7a77708f37..0ffcd2086e 100644
--- a/common/usb_pd_policy.c
+++ b/common/usb_pd_policy.c
@@ -13,7 +13,7 @@
#include "task.h"
#include "timer.h"
#include "util.h"
-#include "usb.h"
+#include "usb_api.h"
#include "usb_pd.h"
#include "usb_pd_config.h"
#include "version.h"
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S
index 9eda0bc8c9..e7df0c2516 100644
--- a/core/cortex-m/ec.lds.S
+++ b/core/cortex-m/ec.lds.S
@@ -19,7 +19,9 @@ MEMORY
FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE
#ifdef CONFIG_USB
- USB_RAM (rw) : ORIGIN = CONFIG_USB_RAM_BASE, LENGTH = CONFIG_USB_RAM_SIZE
+ USB_RAM (rw) : \
+ ORIGIN = CONFIG_USB_RAM_BASE, \
+ LENGTH = CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2
#endif
}
SECTIONS
diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S
index fc858216f2..a72193a7ae 100644
--- a/core/cortex-m0/ec.lds.S
+++ b/core/cortex-m0/ec.lds.S
@@ -19,7 +19,9 @@ MEMORY
FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE
#ifdef CONFIG_USB
- USB_RAM (rw) : ORIGIN = CONFIG_USB_RAM_BASE, LENGTH = CONFIG_USB_RAM_SIZE
+ USB_RAM (rw) : \
+ ORIGIN = CONFIG_USB_RAM_BASE, \
+ LENGTH = CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2
#endif
}
SECTIONS
diff --git a/include/usb.h b/include/usb.h
index d554396ea4..0f2d31f9de 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -10,6 +10,8 @@
#include <stddef.h> /* for wchar_t */
+#include "usb_api.h"
+
#define USB_MAX_PACKET_SIZE 64
/* USB 2.0 chapter 9 definitions */
@@ -226,17 +228,7 @@ struct usb_endpoint_descriptor {
/* Helpers for managing the USB controller dedicated RAM */
/* primitive to access the words in USB RAM */
-#if defined(CHIP_FAMILY_STM32F0)
-typedef uint16_t usb_uint;
-#elif (defined(CHIP_FAMILY_STM32F) || \
- defined(CHIP_FAMILY_STM32L) || \
- defined(CHIP_FAMILY_STM32F3))
-typedef uint32_t usb_uint;
-#elif defined(CHIP_HOST)
-typedef unsigned int usb_uint;
-#else
-#warn "usb_uint not defined for this chip family"
-#endif
+typedef CONFIG_USB_RAM_ACCESS_TYPE usb_uint;
struct stm32_endpoint {
volatile usb_uint tx_addr;
@@ -299,10 +291,4 @@ extern void (*usb_iface_request[]) (usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx);
void IFACE_HANDLER(num)(void) \
__attribute__ ((alias(STRINGIFY(handler))));
-/* functions to start/stop USB */
-void usb_init(void);
-void usb_disconnect(void);
-void usb_connect(void);
-void usb_release(void);
-
#endif /* USB_H */
diff --git a/include/usb_api.h b/include/usb_api.h
new file mode 100644
index 0000000000..feeb6abb27
--- /dev/null
+++ b/include/usb_api.h
@@ -0,0 +1,41 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * USB API definitions.
+ *
+ * This file includes definitions needed by common code that wants to control
+ * the state of the USB peripheral, but doesn't need to know about the specific
+ * implementation.
+ */
+
+#ifndef USB_API_H
+#define USB_API_H
+
+/*
+ * Initialize the USB peripheral, enabling its clock and configuring the DP/DN
+ * GPIOs correctly. This function is called via an init hook, but may need to
+ * be called again if usb_release is called. This function will call
+ * usb_connect by default unless CONFIG_USB_INHIBIT is defined.
+ */
+void usb_init(void);
+
+/*
+ * Enable the pullup on the DP line to signal that this device exists to the
+ * host and to start the enumeration process.
+ */
+void usb_connect(void);
+
+/*
+ * Disable the pullup on the DP line. This causes the device to be disconnected
+ * from the host.
+ */
+void usb_disconnect(void);
+
+/*
+ * Disconnect from the host by calling usb_disconnect and then turn off the USB
+ * peripheral, releasing its GPIOs and disabling its clock.
+ */
+void usb_release(void);
+
+#endif /* USB_API_H */