dingdong: Initial board and USB PD support.

Allows dingdong to receive initial USB PD communication (source
capabilities payload) and with some manual manipulation (see 'TEST=')
drive DPout.

CL is based heavily off hoho dongle where all files were copied from
   board/hoho:
     7b1e58c ectool: Add host command support to set fan RPM for each
             fan separately

   Files gpio.inc, board.h & board.c were modified but others should
   be identical.

BRANCH=none
BUG=chrome-os-partner:31193
TEST=manual,

When attaching dingdong to samus_pd and configured via
  'pd dualrole source'

I see following on samus_pd console:
    C1 st9
    Switch to 5000 V 900 mA (for 900/900 mA)
    C1 st10
    C1 st11
    C1 st12

showing power constract and transition to SRC_RDY:
    > pd 1 state
    Port C1, Enabled - Role: SRC Polarity: CC1 State: SRC_READY

    > typec 1 dp

Also if I connect in CC1 configuration and get access to dingdong
console I can
   > gpioset PD_SBU_ENABLE 1

And see dingdong drive external monitor

Change-Id: I30ef6f8503a3fb015cfb8806bc36fb98f5150e40
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221913
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>

11 files changed, 380 insertions, 4 deletions

diff --git a/board/dingdong/Makefile b/board/dingdong/Makefile
new file mode 120000
index 0000000000..94aaae2c4d
--- /dev/null
+++ b/board/dingdong/Makefile
@@ -0,0 +1 @@
+../../Makefile
\ No newline at end of file
diff --git a/board/dingdong/board.c b/board/dingdong/board.c
new file mode 100644
index 0000000000..70720171a1
--- /dev/null
+++ b/board/dingdong/board.c
@@ -0,0 +1,30 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Dingdong dongle configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "gpio.h"
+#include "registers.h"
+#include "util.h"
+
+#include "gpio_list.h"
+
+/* Initialize board. */
+void board_config_pre_init(void)
+{
+	/* enable SYSCFG clock */
+	STM32_RCC_APB2ENR |= 1 << 0;
+	/* Remap USART DMA to match the USART driver */
+	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
+}
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
+	[ADC_CH_CC1_PD] = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
diff --git a/board/dingdong/board.h b/board/dingdong/board.h
new file mode 100644
index 0000000000..c58a61a769
--- /dev/null
+++ b/board/dingdong/board.h
@@ -0,0 +1,51 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Dingdong dongle configuration */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+/* the UART console is on USART1 (PA9/PA10) */
+#define CONFIG_UART_CONSOLE 1
+
+/* Optional features */
+#define CONFIG_STM_HWTIMER32
+#define CONFIG_ADC
+#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_HW_CRC
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_INTERNAL_COMP
+#undef CONFIG_WATCHDOG_HELP
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_TASK_PROFILING
+
+/*
+ * Allow dangerous commands all the time, since we don't have a write protect
+ * switch.
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_ADC     3
+
+#include "gpio_signal.h"
+
+/* ADC signal */
+enum adc_channel {
+	ADC_CH_CC1_PD = 0,
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __BOARD_H */
diff --git a/board/dingdong/build.mk b/board/dingdong/build.mk
new file mode 100644
index 0000000000..92bb84b52c
--- /dev/null
+++ b/board/dingdong/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F072B
+CHIP:=stm32
+CHIP_FAMILY:=stm32f0
+CHIP_VARIANT:=stm32f07x
+
+board-y=board.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/dingdong/ec.tasklist b/board/dingdong/ec.tasklist
new file mode 100644
index 0000000000..e9c8c1cc1f
--- /dev/null
+++ b/board/dingdong/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD, pd_task, NULL, TASK_STACK_SIZE)
diff --git a/board/dingdong/gpio.inc b/board/dingdong/gpio.inc
new file mode 100644
index 0000000000..67f9d66365
--- /dev/null
+++ b/board/dingdong/gpio.inc
@@ -0,0 +1,27 @@
+/* -*- mode:c -*-
+ *
+ * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+GPIO(DP_HPD,            A, 0,  GPIO_INPUT,    NULL)
+GPIO(USB_C_CC1_PD,      A, 1,  GPIO_ANALOG,   NULL)
+GPIO(PD_DAC_REF,        A, 4,  GPIO_ANALOG,   NULL)
+GPIO(DP_AUX_N,          A, 5,  GPIO_INPUT,    NULL)
+GPIO(DP_AUX_P,          A, 6,  GPIO_INPUT,    NULL)
+
+GPIO(PD_SBU_ENABLE,     A, 8,  GPIO_OUT_LOW,  NULL)
+GPIO(USB_DM,            A, 11, GPIO_ANALOG,   NULL)
+GPIO(USB_DP,            A, 12, GPIO_ANALOG,   NULL)
+GPIO(PD_CC1_TX_EN,      A, 15, GPIO_OUT_LOW,  NULL)
+
+GPIO(PD_DPSINK_PRESENT, B, 0,  GPIO_INPUT,    NULL)
+GPIO(PD_CC1_TX_DATA,    B, 4,  GPIO_OUT_LOW,  NULL)
+
+/* Unimplemented signals which we need to emulate for now */
+UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(WP_L)
+
+ALTERNATE(B, 0x0008, 0, MODULE_USB_PD, 0)            /* SPI1: SCK(PB3) */
+ALTERNATE(B, 0x0200, 2, MODULE_USB_PD, 0)            /* TIM17_CH1: PB9 */
+ALTERNATE(A, 0x0600, 1, MODULE_UART,   GPIO_PULL_UP) /* USART1: PA9/PA10 */
diff --git a/board/dingdong/usb_pd_config.h b/board/dingdong/usb_pd_config.h
new file mode 100644
index 0000000000..4abb3e8d51
--- /dev/null
+++ b/board/dingdong/usb_pd_config.h
@@ -0,0 +1,140 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB Power delivery board configuration */
+
+#ifndef __USB_PD_CONFIG_H
+#define __USB_PD_CONFIG_H
+
+/* Port and task configuration */
+#define PD_PORT_COUNT 1
+#define PORT_TO_TASK_ID(port) TASK_ID_PD
+#define TASK_ID_TO_PORT(id)   0
+
+/* Timer selection for baseband PD communication */
+#define TIM_CLOCK_PD_TX_C0 17
+#define TIM_CLOCK_PD_RX_C0 1
+
+#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
+#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
+
+/* Timer channel */
+#define TIM_RX_CCR_C0 1
+
+/* RX timer capture/compare register */
+#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
+#define TIM_RX_CCR_REG(p) TIM_CCR_C0
+
+/* TX and RX timer register */
+#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
+#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
+#define TIM_REG_TX(p) TIM_REG_TX_C0
+#define TIM_REG_RX(p) TIM_REG_RX_C0
+
+/* use the hardware accelerator for CRC */
+#define CONFIG_HW_CRC
+
+/* TX is using SPI1 on PB3-4 */
+#define SPI_REGS(p) STM32_SPI1_REGS
+
+static inline void spi_enable_clock(int port)
+{
+	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
+}
+
+/* SPI1_TX no remap needed */
+#define DMAC_SPI_TX(p) STM32_DMAC_CH3
+
+/* RX is using COMP1 triggering TIM1 CH1 */
+#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
+#define CMP2OUTSEL 0
+
+#define TIM_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_CCR_CS  1
+#define EXTI_COMP_MASK(p) (1 << 21)
+#define IRQ_COMP STM32_IRQ_COMP
+/* triggers packet detection on comparator falling edge */
+#define EXTI_XTSR STM32_EXTI_FTSR
+
+/* TIM1_CH1 no remap needed */
+#define DMAC_TIM_RX(p) STM32_DMAC_CH2
+
+/* the pins used for communication need to be hi-speed */
+static inline void pd_set_pins_speed(int port)
+{
+	/* 40 Mhz pin speed on TX_EN (PA15) */
+	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xC0000000;
+	/* 40 MHz pin speed on SPI CLK/MOSI (PB3/4) TIM17_CH1 (PB9) */
+	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C03C0;
+}
+
+/* Reset SPI peripheral used for TX */
+static inline void pd_tx_spi_reset(int port)
+{
+	/* Reset SPI1 */
+	STM32_RCC_APB2RSTR |= (1 << 12);
+	STM32_RCC_APB2RSTR &= ~(1 << 12);
+}
+
+/* Drive the CC line from the TX block */
+static inline void pd_tx_enable(int port, int polarity)
+{
+	/* PB4 is SPI1_MISO */
+	gpio_set_alternate_function(GPIO_B, 0x0010, 0);
+
+	gpio_set_level(GPIO_PD_CC1_TX_EN, 1);
+}
+
+/* Put the TX driver in Hi-Z state */
+static inline void pd_tx_disable(int port, int polarity)
+{
+	/* output low on SPI TX (PB4) to disable the FET */
+	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
+				   & ~(3 << (2*4)))
+				   |  (1 << (2*4));
+	/* put the low level reference in Hi-Z */
+	gpio_set_level(GPIO_PD_CC1_TX_EN, 0);
+}
+
+static inline void pd_select_polarity(int port, int polarity)
+{
+	/*
+	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
+	 * use VrefInt / 2 as INM (about 600mV)
+	 */
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
+		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
+}
+
+/* Initialize pins used for TX and put them in Hi-Z */
+static inline void pd_tx_init(void)
+{
+	gpio_config_module(MODULE_USB_PD, 1);
+}
+
+static inline void pd_set_host_mode(int port, int enable) {}
+
+static inline int pd_adc_read(int port, int cc)
+{
+	return adc_read_channel(ADC_CH_CC1_PD);
+}
+
+static inline int pd_snk_is_vbus_provided(int port)
+{
+	return 1;
+}
+
+/* 3.0A DFP : no-connect voltage is 2.45V */
+#define PD_SRC_VNC 2450 /* mV */
+
+/* UFP-side : threshold for DFP connection detection */
+#define PD_SNK_VA   250 /* mV */
+
+/* we are acting only as a sink */
+#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED
+
+/* delay necessary for the voltage transition on the power supply */
+#define PD_POWER_SUPPLY_TRANSITION_DELAY 50000 /* us */
+#endif /* __USB_PD_CONFIG_H */
diff --git a/board/dingdong/usb_pd_policy.c b/board/dingdong/usb_pd_policy.c
new file mode 100644
index 0000000000..57099a960d
--- /dev/null
+++ b/board/dingdong/usb_pd_policy.c
@@ -0,0 +1,90 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "board.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "usb_pd.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+/* Source PDOs */
+const uint32_t pd_src_pdo[] = {};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+/* Fake PDOs : we just want our pre-defined voltages */
+const uint32_t pd_snk_pdo[] = {
+		PDO_FIXED(5000,   500, 0),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+/* Desired voltage requested as a sink (in millivolts) */
+static unsigned select_mv = 5000;
+
+int pd_choose_voltage(int cnt, uint32_t *src_caps, uint32_t *rdo)
+{
+	int i;
+	int ma;
+	int set_mv = select_mv;
+
+	/* Default to 5V */
+	if (set_mv <= 0)
+		set_mv = 5000;
+
+	/* Get the selected voltage */
+	for (i = cnt; i >= 0; i--) {
+		int mv = ((src_caps[i] >> 10) & 0x3FF) * 50;
+		int type = src_caps[i] & PDO_TYPE_MASK;
+		if ((mv == set_mv) && (type == PDO_TYPE_FIXED))
+			break;
+	}
+	if (i < 0)
+		return -EC_ERROR_UNKNOWN;
+
+	/* request all the power ... */
+	ma = 10 * (src_caps[i] & 0x3FF);
+	*rdo = RDO_FIXED(i + 1, ma, ma, 0);
+	ccprintf("Request [%d] %dV %dmA\n", i, set_mv/1000, ma);
+	return ma;
+}
+
+void pd_set_input_current_limit(uint32_t max_ma)
+{
+	/* No battery, nothing to do */
+	return;
+}
+
+void pd_set_max_voltage(unsigned mv)
+{
+	select_mv = mv;
+}
+
+int requested_voltage_idx;
+int pd_request_voltage(uint32_t rdo)
+{
+	return EC_SUCCESS;
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	return EC_SUCCESS;
+}
+
+void pd_power_supply_reset(int port)
+{
+}
+
+int pd_board_checks(void)
+{
+	return EC_SUCCESS;
+}
+
diff --git a/board/hoho/board.c b/board/hoho/board.c
index c30cbfd3a2..35bd123bc5 100644
--- a/board/hoho/board.c
+++ b/board/hoho/board.c
@@ -2,7 +2,7 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-/* Twinkie dongle configuration */
+/* Hoho dongle configuration */
 
 #include "adc.h"
 #include "adc_chip.h"
diff --git a/board/hoho/board.h b/board/hoho/board.h
index a7677d333a..1d330fa4dd 100644
--- a/board/hoho/board.h
+++ b/board/hoho/board.h
@@ -3,7 +3,7 @@
  * found in the LICENSE file.
  */
 
-/* Twinkie dongle configuration */
+/* Hoho dongle configuration */
 
 #ifndef __BOARD_H
 #define __BOARD_H
diff --git a/util/flash_ec b/util/flash_ec
index 56726cd6e4..d4e7df9d16 100755
--- a/util/flash_ec
+++ b/util/flash_ec
@@ -82,8 +82,9 @@ BOARDS_STM32_PROG_EN=(
 )
 
 BOARDS_STM32_DFU=(
-	twinkie
+	dingdong
 	hoho
+	twinkie
 )
 
 # Flags
@@ -243,7 +244,7 @@ function ec_uart() {
 case "${BOARD}" in
 	ryu_sh ) MCU="sh" ;;
 	samus_pd ) MCU="usbpd" ;;
-	twinkie|hoho ) DUT_CONTROL_CMD="true" ; MCU="ec" ;;
+	dingdong|hoho|twinkie ) DUT_CONTROL_CMD="true" ; MCU="ec" ;;
 	*) MCU="ec" ;;
 esac