ish: ensure all CONFIGs are undef'ed in include/config.h

Some people have been bypassing the pre-submit checks:

confs=($(grep -Eor "\bCONFIG_[A-Z_]*" chip/ish/config_chip.h
              | sort | uniq))
for opt in "${confs[@]}"; do
    grep "$opt" include/config.h >/dev/null ||
        echo "$opt is not defined in include/config.h!"
done
>>>
CONFIG_ISH_AON_SRAM_BASE_END is not defined in include/config.h!
CONFIG_ISH_AON_SRAM_BASE_START is not defined in include/config.h!
CONFIG_ISH_AON_SRAM_ROM_SIZE is not defined in include/config.h!
CONFIG_ISH_AON_SRAM_ROM_START is not defined in include/config.h!
CONFIG_ISH_AON_SRAM_SIZE is not defined in include/config.h!
CONFIG_ISH_SRAM_BANKS is not defined in include/config.h!
CONFIG_ISH_SRAM_BANK_SIZE is not defined in include/config.h!
CONFIG_ISH_SRAM_BASE_END is not defined in include/config.h!
CONFIG_ISH_SRAM_BASE_START is not defined in include/config.h!
CONFIG_ISH_SRAM_SIZE is not defined in include/config.h!

This is not good! This commit renames each of these to an existing
option defined in include/config.h, or undefs the relevant option in
include/config.h.

BUG=b:131749055
BRANCH=none
TEST=make buildall -j
TEST=script above reports no options which weren't defined
TEST=arcada_ish, (specifically power management, which was greatly
affected by this commit) functions as normal

Change-Id: Idfbd1105880174b5e160c47c4ec1d88c352d6bc6
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1592420
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1598526
Commit-Queue: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>

6 files changed, 87 insertions, 64 deletions

diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c
index f90ec94d8c..187d073671 100644
--- a/chip/ish/aontaskfw/ish_aontask.c
+++ b/chip/ish/aontaskfw/ish_aontask.c
@@ -172,7 +172,7 @@ void ish_aon_main(void);
 static struct tss_entry aon_tss = {
 	.prev_task_link = 0,
 	.reserved1 = 0,
-	.esp0 = (uint8_t *)(CONFIG_ISH_AON_SRAM_ROM_START - AON_SP_RESERVED),
+	.esp0 = (uint8_t *)(CONFIG_AON_ROM_BASE - AON_SP_RESERVED),
 	/* entry 1 in LDT for data segment */
 	.ss0 = 0xc,
 	.reserved2 = 0,
@@ -191,7 +191,7 @@ static struct tss_entry aon_tss = {
 	.edx = 0,
 	.ebx = 0,
 	/* set stack top pointer at the end of usable aon memory */
-	.esp = CONFIG_ISH_AON_SRAM_ROM_START - AON_SP_RESERVED,
+	.esp = CONFIG_AON_ROM_BASE - AON_SP_RESERVED,
 	.ebp = AON_SP_RESERVED,
 	.esi = 0,
 	.edi = 0,
@@ -295,20 +295,20 @@ static int store_main_fw(void)
 			SNOWBALL_FW_OFFSET +
 			ISH_FW_IMAGE_MANIFEST_HEADER_SIZE;
 
-	imr_fw_rw_addr = imr_fw_addr + aon_share.main_fw_rw_addr -
-			CONFIG_ISH_SRAM_BASE_START;
+	imr_fw_rw_addr = (imr_fw_addr
+			  + aon_share.main_fw_rw_addr
+			  - CONFIG_RAM_BASE);
 
 	/* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */
 	CCU_BCG_EN = CCU_BCG_EN & ~CCU_BCG_BIT_DMA;
 
 	/* store main FW's read and write data region to IMR/UMA DDR */
 	ret = ish_dma_copy(
-			PAGING_CHAN,
-			imr_fw_rw_addr,
-			aon_share.main_fw_rw_addr,
-			aon_share.main_fw_rw_size,
-			SRAM_TO_UMA
-			);
+		PAGING_CHAN,
+		imr_fw_rw_addr,
+		aon_share.main_fw_rw_addr,
+		aon_share.main_fw_rw_size,
+		SRAM_TO_UMA);
 
 	/* enable BCG for DMA, DMA can't be accessed now */
 	CCU_BCG_EN = CCU_BCG_EN | CCU_BCG_BIT_DMA;
@@ -336,23 +336,24 @@ static int restore_main_fw(void)
 			SNOWBALL_FW_OFFSET +
 			ISH_FW_IMAGE_MANIFEST_HEADER_SIZE;
 
-	imr_fw_ro_addr = imr_fw_addr + aon_share.main_fw_ro_addr -
-			CONFIG_ISH_SRAM_BASE_START;
+	imr_fw_ro_addr = (imr_fw_addr
+			  + aon_share.main_fw_ro_addr
+			  - CONFIG_RAM_BASE);
 
-	imr_fw_rw_addr = imr_fw_addr + aon_share.main_fw_rw_addr -
-			CONFIG_ISH_SRAM_BASE_START;
+	imr_fw_rw_addr = (imr_fw_addr
+			  + aon_share.main_fw_rw_addr
+			  - CONFIG_RAM_BASE);
 
 	/* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */
 	CCU_BCG_EN = CCU_BCG_EN & ~CCU_BCG_BIT_DMA;
 
 	/* restore main FW's read only code and data region from IMR/UMA DDR */
 	ret = ish_dma_copy(
-			PAGING_CHAN,
-			aon_share.main_fw_ro_addr,
-			imr_fw_ro_addr,
-			aon_share.main_fw_ro_size,
-			UMA_TO_SRAM
-			);
+		PAGING_CHAN,
+		aon_share.main_fw_ro_addr,
+		imr_fw_ro_addr,
+		aon_share.main_fw_ro_size,
+		UMA_TO_SRAM);
 
 	if (ret != DMA_RC_OK) {
 
@@ -388,12 +389,14 @@ static int restore_main_fw(void)
 	return AON_SUCCESS;
 }
 
-#ifdef CHIP_FAMILY_ISH3
-/* on ISH3, need reserve last SRAM bank for AON use */
-#define SRAM_POWER_OFF_BANKS	(CONFIG_ISH_SRAM_BANKS - 1)
+#if defined(CHIP_FAMILY_ISH3)
+/* on ISH3, the last SRAM bank is reserved for AON use */
+#define SRAM_POWER_OFF_BANKS	(CONFIG_RAM_BANKS - 1)
+#elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5)
+/* ISH4 and ISH5 have separate AON memory, can power off entire main SRAM */
+#define SRAM_POWER_OFF_BANKS	CONFIG_RAM_BANKS
 #else
-/* from ISH4, has seprated AON memory, can power off entire main SRAM  */
-#define SRAM_POWER_OFF_BANKS	CONFIG_ISH_SRAM_BANKS
+#error "CHIP_FAMILY_ISH(3|4|5) must be defined"
 #endif
 
 /**
@@ -435,8 +438,8 @@ static void sram_power(int on)
 	uint32_t sram_addr;
 	uint32_t erase_cfg;
 
-	bank_size = CONFIG_ISH_SRAM_BANK_SIZE;
-	sram_addr = CONFIG_ISH_SRAM_BASE_START;
+	bank_size = CONFIG_RAM_BANK_SIZE;
+	sram_addr = CONFIG_RAM_BASE;
 
 	/**
 	 * set erase size as one bank, erase control register using DWORD as
diff --git a/chip/ish/aontaskfw/ish_aontask.ld.in b/chip/ish/aontaskfw/ish_aontask.ld.in
index 3525519d5b..55ae99a88c 100644
--- a/chip/ish/aontaskfw/ish_aontask.ld.in
+++ b/chip/ish/aontaskfw/ish_aontask.ld.in
@@ -7,8 +7,8 @@
 
 ENTRY(ish_aon_main);
 
-#define SRAM_START  CONFIG_ISH_AON_SRAM_BASE_START
-#define SRAM_RW_LEN (CONFIG_ISH_AON_SRAM_SIZE - CONFIG_ISH_AON_SRAM_ROM_SIZE)
+#define SRAM_START		CONFIG_AON_RAM_BASE
+#define SRAM_RW_LEN		(CONFIG_AON_RAM_SIZE - CONFIG_AON_ROM_SIZE)
 
 /* reserved stack size */
 #define STACK_SIZE  (256)
@@ -37,7 +37,7 @@ MEMORY
 SECTIONS
 {
     /* AON parts visible to FW are linked to the beginning of the AON area */
-    .data.aon_share : AT(CONFIG_ISH_AON_SRAM_BASE_START)
+    .data.aon_share : AT(SRAM_START)
     {
 	KEEP(*(.data.aon_share))
     } > RAM
diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h
index 74432baca1..24cd558f6c 100644
--- a/chip/ish/config_chip.h
+++ b/chip/ish/config_chip.h
@@ -26,45 +26,33 @@
 /* this macro causes 'pause' and reduces loop counts inside loop. */
 #define CPU_RELAX() asm volatile("rep; nop" ::: "memory")
 
-/****************************************************************************/
-/* Memory mapping */
-/****************************************************************************/
+/*****************************************************************************/
+/*                               Memory Layout                               */
+/*****************************************************************************/
 
-/* Define our SRAM layout. */
-#define CONFIG_ISH_SRAM_BASE_START	0xFF000000
-#define CONFIG_ISH_SRAM_BASE_END	0xFF0A0000
-#define CONFIG_ISH_SRAM_SIZE		(CONFIG_ISH_SRAM_BASE_END - \
-					CONFIG_ISH_SRAM_BASE_START)
+#define CONFIG_RAM_BASE		0xFF000000
+#define CONFIG_RAM_SIZE		0x000A0000
+#define CONFIG_RAM_BANK_SIZE		0x00008000
 
 #if defined(CHIP_FAMILY_ISH3)
-/* on ISH3, there is no seprated aon memory, using last 4KB of normal memory
- * without poweroff
- */
-#define CONFIG_ISH_AON_SRAM_BASE_START	0xFF09F000
-#define CONFIG_ISH_AON_SRAM_BASE_END	0xFF0A0000
+/* On ISH3, there is no separate AON memory; use last 4KB of SRAM */
+#define CONFIG_AON_RAM_BASE		0xFF09F000
+#define CONFIG_AON_RAM_SIZE		0x00001000
 #elif defined(CHIP_FAMILY_ISH4)
-#define CONFIG_ISH_AON_SRAM_BASE_START	0xFF800000
-#define CONFIG_ISH_AON_SRAM_BASE_END	0xFF801000
+#define CONFIG_AON_RAM_BASE		0xFF800000
+#define CONFIG_AON_RAM_SIZE		0x00001000
+#elif defined(CHIP_FAMILY_ISH5)
+#define CONFIG_AON_RAM_BASE		0xFF800000
+#define CONFIG_AON_RAM_SIZE		0x00002000
 #else
-#define CONFIG_ISH_AON_SRAM_BASE_START	0xFF800000
-#define CONFIG_ISH_AON_SRAM_BASE_END	0xFF802000
+#error "CHIP_FAMILY_ISH(3|4|5) must be defined"
 #endif
 
-#define CONFIG_ISH_AON_SRAM_SIZE	(CONFIG_ISH_AON_SRAM_BASE_END - \
-					CONFIG_ISH_AON_SRAM_BASE_START)
-
-/* reserve for readonly use in the last of AON memory */
-#define CONFIG_ISH_AON_SRAM_ROM_SIZE    0x80
-#define CONFIG_ISH_AON_SRAM_ROM_START   (CONFIG_ISH_AON_SRAM_BASE_END - \
-					CONFIG_ISH_AON_SRAM_ROM_SIZE)
-
-#define CONFIG_ISH_SRAM_BANK_SIZE	0x8000
-#define CONFIG_ISH_SRAM_BANKS		(CONFIG_ISH_SRAM_SIZE / \
-					CONFIG_ISH_SRAM_BANK_SIZE)
-
-/* Required for panic_output */
-#define CONFIG_RAM_SIZE			CONFIG_ISH_SRAM_SIZE
-#define CONFIG_RAM_BASE			CONFIG_ISH_SRAM_BASE_START
+/* The end of the AON memory is reserved for read-only use */
+#define CONFIG_AON_ROM_SIZE		0x80
+#define CONFIG_AON_ROM_BASE		(CONFIG_AON_RAM_BASE	\
+					 + CONFIG_AON_RAM_SIZE	\
+					 - CONFIG_AON_ROM_SIZE)
 
 /* System stack size */
 #define CONFIG_STACK_SIZE		1024
diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c
index 11b2ba3c3f..663bae61af 100644
--- a/chip/ish/power_mgt.c
+++ b/chip/ish/power_mgt.c
@@ -62,7 +62,7 @@ struct pm_context {
 static struct pm_context pm_ctx = {
 	.aon_valid = 0,
 	/* aon shared data located in the start of aon memory */
-	.aon_share = (struct ish_aon_share *)CONFIG_ISH_AON_SRAM_BASE_START,
+	.aon_share = (struct ish_aon_share *)CONFIG_AON_RAM_BASE,
 	.console_in_use_timeout_sec = 60
 };
 
diff --git a/chip/ish/registers.h b/chip/ish/registers.h
index 7881fd3fe7..b1ead77818 100644
--- a/chip/ish/registers.h
+++ b/chip/ish/registers.h
@@ -343,7 +343,7 @@ enum ish_i2c_port {
 #define SNOWBALL_BASE			IPC_ISH2PMC_MSG_BASE
 #else
 /* from ISH4, used reserved rom part of AON memory */
-#define SNOWBALL_BASE			CONFIG_ISH_AON_SRAM_ROM_START
+#define SNOWBALL_BASE			CONFIG_AON_ROM_BASE
 #endif
 
 /**
diff --git a/include/config.h b/include/config.h
index 67b1b7a1dd..afe67b4b19 100644
--- a/include/config.h
+++ b/include/config.h
@@ -83,6 +83,19 @@
 #undef CONFIG_ACCELGYRO_LSM6DSM
 #undef CONFIG_ACCELGYRO_LSM6DSO
 
+/*
+ * Some chips have a portion of memory which will remain powered even
+ * during a reset.  This is called Always-On, or AON memory, and
+ * typically has a separate firmware to manage the memory.  These
+ * values can be used to configure the RAM layout for Always-On.
+ *
+ * See chip/ish/ for an example implementation.
+ */
+#undef CONFIG_AON_RAM_BASE
+#undef CONFIG_AON_RAM_SIZE
+#undef CONFIG_AON_ROM_BASE
+#undef CONFIG_AON_ROM_SIZE
+
 /* Add sensorhub function for LSM6DSM, required if 2nd device attached. */
 #undef CONFIG_SENSORHUB_LSM6DSM
 
@@ -2747,6 +2760,15 @@
 /* Support Real-Time Clock (RTC) */
 #undef CONFIG_RTC
 
+/* Size of each RAM bank in chip, default is CONFIG_RAM_SIZE */
+#undef CONFIG_RAM_BANK_SIZE
+
+/*
+ * Number of RAM banks in chip, default is
+ * CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE
+ */
+#undef CONFIG_RAM_BANKS
+
 /* Base address of RAM for the chip */
 #undef CONFIG_RAM_BASE
 
@@ -3997,6 +4019,16 @@
 #define CONFIG_DATA_RAM_SIZE	CONFIG_RAM_SIZE
 #endif
 
+/* Automatic configuration of RAM banks **************************************/
+/* Assume one RAM bank if not specified, auto-compute number of banks        */
+#ifndef CONFIG_RAM_BANK_SIZE
+#define CONFIG_RAM_BANK_SIZE	CONFIG_RAM_SIZE
+#endif
+
+#ifndef CONFIG_RAM_BANKS
+#define CONFIG_RAM_BANKS	(CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE)
+#endif
+
 /******************************************************************************/
 /*
  * Set minimum shared memory size, unless it is defined in board file.