mec1322: Fix reset cause detection

Mec1322 cannot distinguish between Power-on and reset condition.
MEC1322_EC_WDT_CNT was used to determine the power-on condition.
VBAT_POR cannot not be used to distinguish no battery condition.
All of the feautures that need support need to determine VCC1_REST
which is used for reset considion. lfw and main code use the same
condition.

When VCC1_RESET is asserted we need to set the image type to
RO image for sysjump to work correctly. This in turn will affect
Recovery mode,software sync and Flashrom. All of these conditions
were tested with this patch.

BUG=chrome-os-partner:40526
TEST=Recovery mode,Software Sync,Flashrom
BRANCH=None

Change-Id: I65f2aa9f56863597116b875ea436d4413887b92b
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283605
Reviewed-by: Shawn N <shawnn@chromium.org>

3 files changed, 11 insertions, 48 deletions

diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c
index cb690fb3e1..1b9e1c4be2 100644
--- a/chip/mec1322/lfw/ec_lfw.c
+++ b/chip/mec1322/lfw/ec_lfw.c
@@ -202,21 +202,13 @@ void uart_init(void)
 void system_init(void)
 {
 
-	uint32_t wdt_cnt = MEC1322_EC_WDT_CNT;
+	uint32_t wdt_sts = MEC1322_VBAT_STS & MEC1322_VBAT_STS_WDT;
 	uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST &
-				(MEC1322_PWR_RST_STS_VCC1 |
-				 MEC1322_PWR_RST_STS_VBAT);
-
-	/*
-	 * BIT[6:5] determine VCC1 reset and VBAT reset status.
-	 * when Poweron watchdog is reset and both VCC1 and VBAT
-	 * are set
-	 */
-	if ((rst_sts == (MEC1322_PWR_RST_STS_VCC1 |
-			 MEC1322_PWR_RST_STS_VBAT))
-			 && (wdt_cnt == 0))
+				MEC1322_PWR_RST_STS_VCC1;
+
+	if (rst_sts || wdt_sts)
 		MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX)
-					= SYSTEM_IMAGE_UNKNOWN;
+					= SYSTEM_IMAGE_RO;
 }
 
 enum system_image_copy_t system_get_image_copy(void)
diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h
index d31b66584b..d1d88d20ac 100644
--- a/chip/mec1322/registers.h
+++ b/chip/mec1322/registers.h
@@ -133,6 +133,9 @@ static inline uintptr_t gpio_port_base(int port_id)
 #define MEC1322_VBAT_CE        REG32(MEC1322_VBAT_BASE + 0x8)
 #define MEC1322_VBAT_RAM(x)    REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x))
 
+/* Bit definition for MEC1322_VBAT_STS */
+#define MEC1322_VBAT_STS_WDT	(1 << 5)
+
 /* Miscellaneous firmware control fields
  * scratch pad index cannot be more than 16 as
  * mec has 64 bytes = 16 indexes of scratchpad RAM
diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c
index e29d8ce247..c753a0ad43 100644
--- a/chip/mec1322/system.c
+++ b/chip/mec1322/system.c
@@ -26,20 +26,6 @@ enum hibdata_index {
 	HIBDATA_INDEX_SAVED_RESET_FLAGS  /* Saved reset flags */
 };
 
-static int check_vcc1_por(void)
-{
-	/*
-	 * WDT count resets on VCC1 POR. If we see WDT count = 0, we know
-	 * POR has occurred, and we set WDT count to 1.
-	 */
-	if (MEC1322_EC_WDT_CNT == 0) {
-		MEC1322_EC_WDT_CNT = 1;
-		return 1;
-	}
-
-	return 0;
-}
-
 static void check_reset_cause(void)
 {
 	uint32_t status = MEC1322_VBAT_STS;
@@ -53,28 +39,16 @@ static void check_reset_cause(void)
 	MEC1322_PCR_CHIP_PWR_RST |= rst_sts;
 
 	/*
-	* BIT[6:5] determine VCC1 reset and VBAT reset status.
-	* when Poweron watchdog is reset and both VCC1 and VBAT
-	* are set
+	* BIT[6] determine VCC1 reset
 	*/
-	if ((rst_sts == (MEC1322_PWR_RST_STS_VCC1 |
-			MEC1322_PWR_RST_STS_VBAT))
-			&& check_vcc1_por())
-		flags |= RESET_FLAG_POWER_ON;
-
-	/*
-	* Check for only BIT 6 to determine VCC1_RST# and no
-	* change on VBAT status indicates this is VCC1_RST#
-	*/
-	if ((rst_sts & MEC1322_PWR_RST_STS_VCC1) &&
-		!(rst_sts & MEC1322_PWR_RST_STS_VBAT))
+	if (rst_sts & MEC1322_PWR_RST_STS_VCC1)
 		flags |= RESET_FLAG_RESET_PIN;
 
 
 	flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
 	MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0;
 
-	if (status & (1 << 5) && !(flags & (RESET_FLAG_SOFT |
+	if ((status & MEC1322_VBAT_STS_WDT) && !(flags & (RESET_FLAG_SOFT |
 					    RESET_FLAG_HARD |
 					    RESET_FLAG_HIBERNATE)))
 		flags |= RESET_FLAG_WATCHDOG;
@@ -114,12 +88,6 @@ void system_pre_init(void)
 	/* Deassert nSIO_RESET */
 	MEC1322_PCR_PWR_RST_CTL &= ~(1 << 0);
 
-	if (MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) &
-		(RESET_FLAG_POWER_ON|RESET_FLAG_RESET_PIN))
-		MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = 0;
-
-	check_reset_cause();
-
 	spi_enable(1);
 }