Initial McCroskey support

This adds a board target for McCroskey. It is loosely based on
Snow.

The clock will be set up differently and the keyboard GPIOs are
not the same, so some stm32 code needed to be updated.

BUG=none
BRANCH=none
TEST=tested on McCroskey (we get to the serial console)
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I5e11a3257fed1797f4cc4dcccf3530585b78da82
Reviewed-on: https://gerrit.chromium.org/gerrit/43414
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>

6 files changed, 346 insertions, 8 deletions

diff --git a/board/mccroskey/board.c b/board/mccroskey/board.c
new file mode 100644
index 0000000000..b6d7de815a
--- /dev/null
+++ b/board/mccroskey/board.c
@@ -0,0 +1,161 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* McCroskey board-specific configuration */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "dma.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "registers.h"
+#include "spi.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#define GPIO_OUTPUT_OD (GPIO_OUTPUT | GPIO_OPEN_DRAIN)
+#define GPIO_KB_INPUT  (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
+#define GPIO_KB_OUTPUT GPIO_OUTPUT_OD
+
+#define HARD_RESET_TIMEOUT_MS 5
+
+static void kbd_power_on(enum gpio_signal signal);
+
+/* GPIO signal list.  Must match order from enum gpio_signal. */
+const struct gpio_info gpio_list[GPIO_COUNT] = {
+	/* Inputs with interrupt handlers are first for efficiency */
+	{"KB_IN00",        GPIO_B, (1<<8),  GPIO_KB_INPUT, matrix_interrupt},
+	{"KB_IN01",        GPIO_B, (1<<9),  GPIO_KB_INPUT, matrix_interrupt},
+	{"KB_IN02",        GPIO_B, (1<<10), GPIO_KB_INPUT, matrix_interrupt},
+	{"KB_IN03",        GPIO_B, (1<<11), GPIO_KB_INPUT, matrix_interrupt},
+	{"KB_IN04",        GPIO_B, (1<<12), GPIO_KB_INPUT, matrix_interrupt},
+	{"KB_IN05",        GPIO_B, (1<<13), GPIO_KB_INPUT, matrix_interrupt},
+	{"KB_IN06",        GPIO_B, (1<<14), GPIO_KB_INPUT, matrix_interrupt},
+	{"KB_IN07",        GPIO_B, (1<<15), GPIO_KB_INPUT, matrix_interrupt},
+	{"KBD_PWR_BUTTON", GPIO_B, (1<<2),  GPIO_INPUT, kbd_power_on},
+
+	{"OMZO_RDY_L",     GPIO_A, (1<<0),  GPIO_INPUT, NULL},	/* PA0_WKUP */
+	{"OZMO_RST_L",     GPIO_A, (1<<2),  GPIO_OUTPUT_OD, NULL},
+	{"VBUS_UP_DET",    GPIO_A, (1<<3),  GPIO_INPUT, NULL},
+	{"OZMO_REQ_L",     GPIO_A, (1<<8),  GPIO_INPUT, NULL},
+	{"CHARGE_ZERO",    GPIO_B, (1<<0),  GPIO_INPUT, NULL},
+	{"CHARGE_SHUNT",   GPIO_B, (1<<1),  GPIO_INPUT, NULL},
+	{"PMIC_INT_L",     GPIO_B, (1<<5),  GPIO_INPUT, NULL},
+
+	/*
+	 * I2C pins should be configured as inputs until I2C module is
+	 * initialized. This will avoid driving the lines unintentionally.
+	 */
+	{"I2C1_SCL",       GPIO_B, (1<<6),  GPIO_INPUT, NULL},
+	{"I2C1_SDA",       GPIO_B, (1<<7),  GPIO_INPUT, NULL},
+
+	{"KB_OUT00",       GPIO_C, (1<<0),  GPIO_KB_OUTPUT, NULL},
+	{"KB_OUT01",       GPIO_C, (1<<1),  GPIO_KB_OUTPUT, NULL},
+	{"KB_OUT02",       GPIO_C, (1<<2),  GPIO_KB_OUTPUT, NULL},
+	{"KB_OUT03",       GPIO_C, (1<<3),  GPIO_KB_OUTPUT, NULL},
+	{"KB_OUT04",       GPIO_C, (1<<4),  GPIO_KB_OUTPUT, NULL},
+	{"KB_OUT05",       GPIO_C, (1<<5),  GPIO_KB_OUTPUT, NULL},
+	{"KB_OUT06",       GPIO_C, (1<<6),  GPIO_KB_OUTPUT, NULL},
+	{"KB_OUT07",       GPIO_C, (1<<7),  GPIO_KB_OUTPUT, NULL},
+	{"KB_OUT08",       GPIO_C, (1<<8),  GPIO_KB_OUTPUT, NULL},
+	{"KB_OUT09",       GPIO_C, (1<<9),  GPIO_KB_OUTPUT, NULL},
+	{"KB_OUT10",       GPIO_C, (1<<10), GPIO_KB_OUTPUT, NULL},
+	{"KB_OUT11",       GPIO_C, (1<<11), GPIO_KB_OUTPUT, NULL},
+	{"KB_OUT12",       GPIO_C, (1<<12), GPIO_KB_OUTPUT, NULL},
+	{"USB_VBUS_CTRL",  GPIO_C, (1<<13), GPIO_OUTPUT, NULL},
+	{"HUB_RESET",      GPIO_C, (1<<14), GPIO_OUTPUT_OD, NULL},
+	{"WP_L",           GPIO_D, (1<<2),  GPIO_INPUT, NULL},
+
+	/* FIXME: make this alt. function */
+	{"BL_PWM",         GPIO_A, (1<<1),  GPIO_OUTPUT, NULL},
+#if 0
+	/* Other GPIOs (probably need to be set up below as alt. function) */
+	{"STM_USBDM",      GPIO_A, (1<<11), GPIO_DEFAULT, NULL},
+	{"STM_USBDP",      GPIO_A, (1<<12), GPIO_DEFAULT, NULL},
+	{"JTMS_SWDIO",     GPIO_A, (1<<13), GPIO_DEFAULT, NULL},
+	{"JTCK_SWCLK",     GPIO_A, (1<<14), GPIO_DEFAULT, NULL},
+	{"JTDI",           GPIO_A, (1<<15), GPIO_DEFAULT, NULL},
+	{"JTDO",           GPIO_B, (1<<3),  GPIO_DEFAULT, NULL},
+	{"JNTRST",         GPIO_B, (1<<4),  GPIO_DEFAULT, NULL},
+	{"OSC32_OUT",      GPIO_C, (1<<15), GPIO_DEFAULT, NULL},
+#endif
+};
+
+void configure_board(void)
+{
+	uint32_t val;
+
+	dma_init();
+
+	/* Enable all GPIOs clocks
+	 * TODO: more fine-grained enabling for power saving
+	 */
+	STM32_RCC_APB2ENR |= 0x1fd;
+
+#ifdef CONFIG_SPI
+	/* Enable SPI */
+	STM32_RCC_APB2ENR |= (1<<12);
+
+	/* SPI1 on pins PA4-7 (alt. function push-pull, 10MHz) */
+	/* FIXME: Connected device SPI freq is fxo/2 in master mode, fxo/4
+	 * in slave mode. fxo ranges from 12-40MHz */
+	val = STM32_GPIO_CRL_OFF(GPIO_A) & ~0xffff0000;
+	val |= 0x99990000;
+	STM32_GPIO_CRL_OFF(GPIO_A) = val;
+#endif
+
+	/* remap OSC_IN/OSC_OUT to PD0/PD1 */
+	STM32_GPIO_AFIO_MAPR |= 1 << 15;
+
+	/* use PB3 as a GPIO, so disable JTAG and keep only SWD */
+	STM32_GPIO_AFIO_MAPR = (STM32_GPIO_AFIO_MAPR & ~(0x7 << 24))
+			       | (2 << 24);
+
+	/* remap TIM2_CH2 to PB3 */
+	STM32_GPIO_AFIO_MAPR = (STM32_GPIO_AFIO_MAPR & ~(0x3 << 8))
+			       | (1 << 8);
+
+	/*
+	 * Set alternate function for USART1. For alt. function input
+	 * the port is configured in either floating or pull-up/down
+	 * input mode (ref. section 7.1.4 in datasheet RM0041):
+	 * PA9:  Tx, alt. function output
+	 * PA10: Rx, input with pull-down
+	 *
+	 * note: see crosbug.com/p/12223 for more info
+	 */
+	val = STM32_GPIO_CRH_OFF(GPIO_A) & ~0x00000ff0;
+	val |= 0x00000890;
+	STM32_GPIO_CRH_OFF(GPIO_A) = val;
+}
+
+/* GPIO configuration to be done after I2C module init */
+void board_i2c_post_init(int port)
+{
+	uint32_t val;
+
+	/* enable alt. function (open-drain) */
+	if (port == STM32_I2C1_PORT) {
+		/* I2C1 is on PB6-7 */
+		val = STM32_GPIO_CRL_OFF(GPIO_B) & ~0xff000000;
+		val |= 0xdd000000;
+		STM32_GPIO_CRL_OFF(GPIO_B) = val;
+	}
+}
+
+void system_warm_reboot(void)
+{
+	/* FIXME: this is just a stub for now... */
+}
+
+void kbd_power_on(enum gpio_signal signal)
+{
+	/* FIXME: this is just a stub for now... */
+}
+
+/* FIXME: this should not be needed on mccroskey. */
+void board_interrupt_host(int active) { }
diff --git a/board/mccroskey/board.h b/board/mccroskey/board.h
new file mode 100644
index 0000000000..28ce13444e
--- /dev/null
+++ b/board/mccroskey/board.h
@@ -0,0 +1,127 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* McCroskey board configuration */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/* 48 MHz SYSCLK clock frequency */
+/*
+ * FIXME(dhendrix): We'll eventually switch to the HSE instead of HSI.
+ * Also, I2C is limited to 2-36MHz, so for now let's just use 16MHz until
+ * we're ready to switch to the HSE. FREQ in I2C1 CR2 also must be set
+ * appropriately.
+ */
+#define CPU_CLOCK 48000000	/* should be 48000000 */
+
+/* Use USART1 as console serial port */
+#define CONFIG_CONSOLE_UART 1
+
+/* Debug features */
+#define CONFIG_PANIC_HELP
+#define CONFIG_ASSERT_HELP
+#define CONFIG_CONSOLE_CMDHELP
+
+#undef  CONFIG_TASK_PROFILING
+#define CONFIG_WATCHDOG_HELP
+
+/* use STOP mode when we have nothing to do */
+/*
+ * FIXME(dhendrix): This causes the UART to drop characters and likely
+ * other bad side-effects. Disable for now.
+ */
+#if 0
+#define CONFIG_LOW_POWER_IDLE
+#endif
+
+#ifndef __ASSEMBLER__
+
+/* By default, enable all console messages except keyboard */
+#define CC_DEFAULT	(CC_ALL)
+
+#define USB_CHARGE_PORT_COUNT 0
+
+/* EC drives 13 outputs to the keyboard matrix and reads 8 inputs/interrupts */
+#define KB_INPUTS 8
+#define KB_OUTPUTS 13
+#define KB_OUT_PORT_LIST GPIO_C
+
+/* EC is I2C master */
+#define CONFIG_I2C
+#define I2C_PORT_HOST 0
+#define I2C_PORT_SLAVE 0	/* needed for DMAC macros (ugh) */
+#define CONFIG_DEBUG_I2C	/* FIXME(dhendrix): remove this eventually */
+#define GPIO_I2C2_SCL 0		/* unused, but must be defined anyway */
+#define GPIO_I2C2_SDA 0		/* unused, but must be defined anyway */
+
+/* Timer selection */
+#define TIM_CLOCK_MSB 3
+#define TIM_CLOCK_LSB 4
+
+/* GPIO signal list */
+enum gpio_signal {
+	GPIO_KB_IN00,
+	GPIO_KB_IN01,
+	GPIO_KB_IN02,
+	GPIO_KB_IN03,
+	GPIO_KB_IN04,
+	GPIO_KB_IN05,
+	GPIO_KB_IN06,
+	GPIO_KB_IN07,
+	GPIO_KBD_PWR_BUTTON,
+	GPIO_OMZO_RDY_L,
+	GPIO_OZMO_RST_L,
+	GPIO_VBUS_UP_DET,
+	GPIO_OZMO_REQ_L,
+	GPIO_CHARGE_ZERO,
+	GPIO_CHARGE_SHUNT,
+	GPIO_PMIC_INT_L,
+	GPIO_I2C1_SCL,
+	GPIO_I2C1_SDA,
+	GPIO_KB_OUT00,
+	GPIO_KB_OUT01,
+	GPIO_KB_OUT02,
+	GPIO_KB_OUT03,
+	GPIO_KB_OUT04,
+	GPIO_KB_OUT05,
+	GPIO_KB_OUT06,
+	GPIO_KB_OUT07,
+	GPIO_KB_OUT08,
+	GPIO_KB_OUT09,
+	GPIO_KB_OUT10,
+	GPIO_KB_OUT11,
+	GPIO_KB_OUT12,
+	GPIO_USB_VBUS_CTRL,
+	GPIO_HUB_RESET,
+	GPIO_WRITE_PROTECTn,
+
+	/* FIXME: this will be an alt. function GPIO, so remove it from here */
+	GPIO_BL_PWM,
+#if 0
+	GPIO_STM_USBDM,
+	GPIO_STM_USBDP,
+	GPIO_JTMS_SWDIO,
+	GPIO_JTCK_SWCLK,
+	GPIO_JTDI,
+	GPIO_JTDO,
+	GPIO_JNTRST,
+	GPIO_OSC32_OUT,
+#endif
+	GPIO_COUNT
+};
+
+void configure_board(void);
+
+void matrix_interrupt(enum gpio_signal signal);
+
+/* FIXME: this should not be needed on mccroskey. */
+void board_interrupt_host(int active);
+
+void system_warm_reboot(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __BOARD_H */
diff --git a/board/mccroskey/build.mk b/board/mccroskey/build.mk
new file mode 100644
index 0000000000..aedcb384eb
--- /dev/null
+++ b/board/mccroskey/build.mk
@@ -0,0 +1,13 @@
+# -*- makefile -*-
+# Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F102R8
+CHIP:=stm32
+
+CHIP_VARIANT:=stm32f10x
+
+board-y=board.o
diff --git a/board/mccroskey/ec.tasklist b/board/mccroskey/ec.tasklist
new file mode 100644
index 0000000000..dab971ccb3
--- /dev/null
+++ b/board/mccroskey/ec.tasklist
@@ -0,0 +1,21 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK(n, r, d, s) where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+	TASK(TICK, hook_task, NULL, TASK_STACK_SIZE) \
+	TASK(KEYSCAN, keyboard_scan_task, NULL, 360) \
+	TASK(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
+	TASK(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE)
diff --git a/chip/stm32/clock-stm32f100.c b/chip/stm32/clock-stm32f100.c
index 1e99e78248..b3046c39d6 100644
--- a/chip/stm32/clock-stm32f100.c
+++ b/chip/stm32/clock-stm32f100.c
@@ -123,6 +123,25 @@ static void __rtc_alarm_irq(void)
 }
 DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1);
 
+#if defined(BOARD_daisy) || defined(BOARD_snow) || defined(BOARD_spring)
+/*
+ * stays on HSI (8MHz), no prescaler, PLLSRC = HSI/2, PLLMUL = x4
+ * no MCO                      => PLLCLK = 16 Mhz
+ */
+#define DESIRED_CPU_CLOCK 16000000
+#define RCC_CFGR 0x00080000
+#elif defined(BOARD_mccroskey)
+/*
+ * HSI = 8MHz, no prescaler, no MCO
+ * PLLSRC = HSI/2, PLLMUL = x12 => PLLCLK = 48MHz
+ * USB clock = PLLCLK
+ */
+#define DESIRED_CPU_CLOCK 48000000
+#define RCC_CFGR 0x00680000
+#else
+#error "Need board-specific clock settings"
+#endif
+
 static void config_hispeed_clock(void)
 {
 	/* Ensure that HSI is ON */
@@ -134,19 +153,16 @@ static void config_hispeed_clock(void)
 			;
 	}
 
-	/*
-	 * stays on HSI (8MHz), no prescaler, PLLSRC = HSI/2, PLLMUL = x4
-	 * no MCO                      => PLLCLK = 16 Mhz
-	 */
-	BUILD_ASSERT(CPU_CLOCK == 16000000);
-	STM32_RCC_CFGR = 0x00080000;
+	BUILD_ASSERT(CPU_CLOCK == DESIRED_CPU_CLOCK);
+	STM32_RCC_CFGR = RCC_CFGR;
 	/* Enable the PLL */
 	STM32_RCC_CR |= 1 << 24;
 	/* Wait for the PLL to lock */
 	while (!(STM32_RCC_CR & (1 << 25)))
 		;
 	/* switch to SYSCLK to the PLL */
-	STM32_RCC_CFGR = 0x00080002;
+	STM32_RCC_CFGR = RCC_CFGR | 0x02;
+
 	/* wait until the PLL is the clock source */
 	while ((STM32_RCC_CFGR & 0xc) != 0x8)
 		;
diff --git a/chip/stm32/config-stm32f10x.h b/chip/stm32/config-stm32f10x.h
index 8e21103dc5..23c7ba411b 100644
--- a/chip/stm32/config-stm32f10x.h
+++ b/chip/stm32/config-stm32f10x.h
@@ -5,7 +5,7 @@
 
 /* Memory mapping */
 #define CONFIG_FLASH_BASE       0x08000000
-#define CONFIG_FLASH_PHYSICAL_SIZE 0x00010000
+#define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000
 #define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */