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| author | Jun Lin <CHLin56@nuvoton.com> | 2021-04-29 14:31:33 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-05-04 02:39:08 +0000 |
| commit | 14dd51f4fcfeb1bbbdbf0dd9f9365c4072db44ef (patch) | |
| tree | 196ceee7688b398a4796f5fce2cfe2195e38c29b | |
| parent | af432dbd2c5ba0e979549b4b9bad8edbf414bda3 (diff) | |
| download | chrome-ec-14dd51f4fcfeb1bbbdbf0dd9f9365c4072db44ef.tar.gz | |
Port80: allow to accept 4-byte Port80 code
The original Port80 implementation assumes that the Port80 code is
only 2-byte wide and is less than 0x100. In the recent AMD chipset
(CEZANNE), AP will send a 4-byte Port80 code via a single PUT_IOWR_SHORT
eSPI transaction in PSP. This CL adds a config option to allow the
Port80 to print 4-byte code when the config is defined.
BRANCH=none
BUG=b:184872297
TEST=build the image with "#define CONFIG_PORT80_4_BYTE";
connect npcx9_evb to the eSPI host emulator; the host sends a
PUT_IOWR_SHORT transaction to IO address 0x80 with 4 bytes of code
"0xEEE20400"; the EC console shows:
Port 80 writes:
eee20400 <--new
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I3b93d9fc41e1875bb628a15c58231005e9555cfd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2858296
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
| -rw-r--r-- | common/port80.c | 15 | ||||
| -rw-r--r-- | include/config.h | 6 |
2 files changed, 16 insertions, 5 deletions
diff --git a/common/port80.c b/common/port80.c index 52264cc446..c2ad87f38f 100644 --- a/common/port80.c +++ b/common/port80.c @@ -17,9 +17,14 @@ #define CPRINTF(format, args...) cprintf(CC_PORT80, format, ## args) -static uint16_t __bss_slow history[CONFIG_PORT80_HISTORY_LEN]; +#ifdef CONFIG_PORT80_4_BYTE +typedef uint32_t port80_code_t; +#else +typedef uint16_t port80_code_t; +#endif +static port80_code_t __bss_slow history[CONFIG_PORT80_HISTORY_LEN]; static int __bss_slow writes; /* Number of port 80 writes so far */ -static int last_boot; /* Last code from previous boot */ +static port80_code_t last_boot; /* Last code from previous boot */ static int __bss_slow scroll; #ifdef CONFIG_BRINGUP @@ -55,15 +60,15 @@ void port_80_write(int data) if (print_in_int) CPRINTF("%c[%pT Port 80: 0x%02x]", scroll ? '\n' : '\r', PRINTF_TIMESTAMP_NOW, data); - else if (data < 0x100) + else if (data < 0x100 || IS_ENABLED(CONFIG_PORT80_4_BYTE)) hook_call_deferred(&port80_dump_buffer_data, 4 * SECOND); /* Save current port80 code if system is resetting */ if (data == PORT_80_EVENT_RESET && writes) { - int prev = history[(writes-1) % ARRAY_SIZE(history)]; + port80_code_t prev = history[(writes-1) % ARRAY_SIZE(history)]; /* Ignore special event codes */ - if (prev < 0x100) + if (prev < 0x100 || IS_ENABLED(CONFIG_PORT80_4_BYTE)) last_boot = prev; } diff --git a/include/config.h b/include/config.h index 8dc2d0aa5a..b6f48c741a 100644 --- a/include/config.h +++ b/include/config.h @@ -3270,6 +3270,12 @@ */ #define CONFIG_PORT80_PRINT_IN_INT 0 +/* + * Allow Port80 common layer to dump 4-byte Port80 code. This is only supported + * on NPCX9 (and latter) chips. + */ +#undef CONFIG_PORT80_4_BYTE + /* MAX695x 7 segment driver */ #undef CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY |