diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2020-08-25 10:56:43 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-08-27 18:55:21 +0000 |
| commit | 7e894e7e180d62d26fb81804709aa7ff8f958e17 (patch) | |
| tree | c28c7b9c516da8bf918a0c5a2264f955f660fc15 | |
| parent | b7707a936c79d86d6e57534ca6125acb7021e2f5 (diff) | |
| download | chrome-ec-7e894e7e180d62d26fb81804709aa7ff8f958e17.tar.gz | |
it83xx/system: Don't disable DBGR in system reset
Our current implementation will disable DBGR (debug mode) in system
reset, but this will break flashing sequence. So we make a change to
ensure flashing won't be broken under the above situation.
Note: DBGR is only applied to flashing sequence, a HW reset after
flashing will disable DBGR and allow normal system reset.
We also enable wait flashing sequence in this CL, so EC can check if
there’s a DBGR flag during initialization and proceed afterwards.
BUG=b:118584434, b:165515400
BRANCH=none
TEST=- The soft reset still works after flashing.
- EC can be flashed even if it is in continuous reboot loop.
Change-Id: I9cea2c4fef74de7afcffb203e02f79cb18a4c5bf
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1243878
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | chip/it83xx/registers.h | 2 | ||||
| -rw-r--r-- | chip/it83xx/system.c | 28 |
2 files changed, 21 insertions, 9 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 56a4500bf6..3c7202a698 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -963,6 +963,8 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE+0x01) #endif #define IT83XX_GCTRL_CHIPVER REG8(IT83XX_GCTRL_BASE+0x02) +#define IT83XX_GCTRL_DBGROS REG8(IT83XX_GCTRL_BASE+0x03) +#define IT83XX_SMB_DBGR BIT(0) #define IT83XX_GCTRL_WNCKR REG8(IT83XX_GCTRL_BASE+0x0B) #define IT83XX_GCTRL_RSTS REG8(IT83XX_GCTRL_BASE+0x06) #define IT83XX_GCTRL_BADRSEL REG8(IT83XX_GCTRL_BASE+0x0A) diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c index 615f89de9d..960ef7b622 100644 --- a/chip/it83xx/system.c +++ b/chip/it83xx/system.c @@ -161,8 +161,19 @@ int system_is_reboot_warm(void) void chip_pre_init(void) { - /* bit4, enable debug mode through SMBus */ - IT83XX_SMB_SLVISELR &= ~BIT(4); + /* bit0, EC received the special waveform from iteflash */ + if (IT83XX_GCTRL_DBGROS & IT83XX_SMB_DBGR) { + /* + * Wait ~200ms, so iteflash will have enough time to let + * EC enter follow mode. And once EC goes into follow mode, EC + * will be stayed here (no following sequences, eg: + * enable watchdog/write protect/power-on sequence...) until + * we reset it. + */ + for (int i = 0; i < (200 * MSEC / 15); i++) + /* delay ~15.25us */ + IT83XX_GCTRL_WNCKR = 0; + } if (IS_ENABLED(IT83XX_ETWD_HW_RESET_SUPPORT)) /* System triggers a soft reset by default (command: reboot). */ @@ -231,6 +242,12 @@ void system_reset(int flags) { uint32_t save_flags = 0; + /* We never get this warning message in normal case. */ + if (IT83XX_GCTRL_DBGROS & IT83XX_SMB_DBGR) { + ccprintf("!Reset will be failed due to EC is in debug mode!\n"); + cflush(); + } + /* Disable interrupts to avoid task swaps during reboot. */ interrupt_disable(); @@ -254,13 +271,6 @@ void system_reset(int flags) } } - /* - * bit4, disable debug mode through SMBus. - * If we are in debug mode, we need disable it before triggering - * a soft reset or reset will fail. - */ - IT83XX_SMB_SLVISELR |= BIT(4); - /* bit0: enable watchdog hardware reset. */ #ifdef IT83XX_ETWD_HW_RESET_SUPPORT if (flags & SYSTEM_RESET_HARD) |