zephyr: mchp: Support adlrvp_mchp project

Support adlrvp_mchp project, run on Intel ADL RVP with
mec1727 MECC card, pass ADL required FAFT.

BUG=none
BRANCH=main
TEST=zmake build adlrvp_mchp, verify following functions on RVP
-- Power on / off sequence: S0/S3/S5/G3;
-- Boot up to Chromium OS;
-- UART console;
-- Battery and charger via I2C interface;
-- Keyscan matrix;
-- Power button / LID / AC present switches;
-- WDT;
-- 512KB SPI RO/RW images for EC Rom loader;
-- Sysjump RW/RO and hash;
-- System hibernate;
-- Flash access - flashread / flashwrite / flasherase;
-- Rebase on 10/18/2022;

Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: I43dfd24c92126b59956e5d0192b1f62b8b05e798
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3606924
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>

11 files changed, 842 insertions, 2 deletions

diff --git a/zephyr/projects/.pylintrc b/zephyr/projects/.pylintrc
index f4609e3781..8bdb6378e4 100644
--- a/zephyr/projects/.pylintrc
+++ b/zephyr/projects/.pylintrc
@@ -4,6 +4,7 @@ additional-builtins=
     register_binman_project,
     register_host_project,
     register_host_test,
+    register_mchp_project,
     register_npcx_project,
     register_raw_project,
 good-names=BUILD
diff --git a/zephyr/projects/intelrvp/BUILD.py b/zephyr/projects/intelrvp/BUILD.py
index e6e617ea23..f129b3d2d2 100644
--- a/zephyr/projects/intelrvp/BUILD.py
+++ b/zephyr/projects/intelrvp/BUILD.py
@@ -15,7 +15,9 @@ def register_intelrvp_project(
 ):
     """Register a variant of intelrvp."""
     register_func = register_binman_project
-    if chip.startswith("npcx"):
+    if chip.startswith("mec1727"):
+        register_func = register_mchp_project
+    elif chip.startswith("npcx"):
         register_func = register_npcx_project
 
     kconfig_files = [here / "prj.conf"]
@@ -39,6 +41,23 @@ def register_intelrvp_project(
 
 
 register_intelrvp_project(
+    project_name="adlrvp_mchp",
+    chip="mec1727",
+    extra_dts_overlays=[
+        here / "adlrvp/adlrvp_mchp/adlrvp_mchp.dts",
+        here / "adlrvp/adlrvp_mchp/gpio.dts",
+        here / "adlrvp/adlrvp_mchp/interrupts.dts",
+        here / "adlrvp/adlrvp_mchp/keyboard.dts",
+        here / "adlrvp/adlrvp_mchp/usbc.dts",
+    ],
+    extra_kconfig_files=[
+        here / "legacy_ec_pwrseq.conf",
+        here / "adlrvp/adlrvp_mchp/prj.conf",
+    ],
+)
+
+
+register_intelrvp_project(
     project_name="adlrvp_npcx",
     chip="npcx9m7f",
     extra_dts_overlays=[
@@ -57,6 +76,7 @@ register_intelrvp_project(
     ],
 )
 
+
 register_intelrvp_project(
     project_name="mtlrvpp_npcx",
     chip="npcx9m3f",
diff --git a/zephyr/projects/intelrvp/CMakeLists.txt b/zephyr/projects/intelrvp/CMakeLists.txt
index 25b3af3931..039627dec6 100644
--- a/zephyr/projects/intelrvp/CMakeLists.txt
+++ b/zephyr/projects/intelrvp/CMakeLists.txt
@@ -14,7 +14,7 @@ cros_ec_library_include_directories("${PLATFORM_EC}/driver/tcpm")
 cros_ec_library_include_directories("${PLATFORM_EC}/driver/usb_mux")
 zephyr_library_sources("src/intel_rvp_board_id.c")
 
-if(DEFINED CONFIG_BOARD_ADLRVP_NPCX)
+if((DEFINED CONFIG_BOARD_ADLRVP_MCHP) OR (DEFINED CONFIG_BOARD_ADLRVP_NPCX))
   add_subdirectory(adlrvp)
   zephyr_library_sources("src/intelrvp.c")
   zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "${PLATFORM_EC}/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c")
diff --git a/zephyr/projects/intelrvp/Kconfig b/zephyr/projects/intelrvp/Kconfig
index c51c54847b..605f57c054 100644
--- a/zephyr/projects/intelrvp/Kconfig
+++ b/zephyr/projects/intelrvp/Kconfig
@@ -2,6 +2,13 @@
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
+config BOARD_ADLRVP_MCHP
+	bool "Intel ADLRVP_MCHP board"
+	depends on SOC_MEC172X_NSZ
+	help
+	  Build Intel ADLRVP_MCHP reference board. This board has Intel ADL RVP
+	  SoC with MEC1727 EC.
+
 config BOARD_ADLRVP_NPCX
 	bool "Intel ADLRVP_NPCX board"
 	depends on SOC_NPCX9M7F
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/adlrvp_mchp.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/adlrvp_mchp.dts
new file mode 100644
index 0000000000..527a62e776
--- /dev/null
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/adlrvp_mchp.dts
@@ -0,0 +1,201 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_ac_present
+			&int_lid_open
+			&int_power_button
+		>;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_charger: charger {
+			i2c-port = <&i2c_smb_0>;
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_CHARGER",
+				"I2C_PORT_EEPROM",
+				"I2C_PORT_PORT80";
+		};
+		typec_0: typec-0 {
+			i2c-port = <&i2c_smb_1>;
+			enum-names = "I2C_PORT_TYPEC_0";
+		};
+		typec_1: typec-1 {
+			i2c-port = <&i2c_smb_2>;
+			enum-names = "I2C_PORT_TYPEC_1";
+		};
+		typec_2: typec-2 {
+			i2c-port = <&i2c_smb_3>;
+			enum-names = "I2C_PORT_TYPEC_2";
+		};
+		typec_3: typec-3 {
+			i2c-port = <&i2c_smb_4>;
+			enum-names = "I2C_PORT_TYPEC_3";
+		};
+	};
+};
+
+/* charger */
+&i2c_smb_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	port_sel = <0>;
+	pinctrl-0 = <&i2c00_scl_gpio004 &i2c00_sda_gpio003>;
+	pinctrl-names = "default";
+
+	pca95xx: pca95xx@22 {
+		compatible = "nxp,pca95xx";
+		label = "PCA95XX";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <16>;
+	};
+
+	rvp_board_id: rvp-board-id {
+		compatible = "intel,rvp-board-id";
+
+		/*
+		 * BOM ID [2]   : IOEX[0]
+		 * BOM ID [1:0] : IOEX[15:14]
+		 */
+		bom-gpios = <&pca95xx 0 0>, <&pca95xx 15 0>, <&pca95xx 14 0>;
+
+		/*
+		 * FAB ID [1:0] : IOEX[2:1]
+		 */
+		fab-gpios = <&pca95xx 2 0>, <&pca95xx 1 0>;
+
+		/*
+		 * BOARD ID[5:0] : IOEX[13:8]
+		 */
+		board-gpios = <&pca95xx 13 0>, <&pca95xx 12 0>, <&pca95xx 11 0>,
+			      <&pca95xx 10 0>, <&pca95xx 9 0>, <&pca95xx 8 0>;
+	};
+
+	seven_seg_display: max695x-seven-seg-display@38 {
+		compatible = "maxim,seven-seg-display";
+		reg = <0x38>;
+		label = "MAX695X_SEVEN_SEG_DISPLAY";
+	};
+
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+/* typec_0 */
+&i2c_smb_1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	port_sel = <6>;
+	pinctrl-0 = <&i2c06_scl_gpio140 &i2c06_sda_gpio132>;
+	pinctrl-names = "default";
+
+	tcpc_port0: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+	};
+
+	usb_c0_soc_side_bb_retimer: jhl8040r-c0-soc-side@54 {
+		compatible = "intel,jhl8040r";
+		reg = <0x54>;
+		reset-pin = <&usb_c0_bb_retimer_rst>;
+		ls-en-pin = <&usb_c0_bb_retimer_ls_en>;
+	};
+
+	usb_c0_bb_retimer: jhl8040r-c0@56 {
+		compatible = "intel,jhl8040r";
+		reg = <0x56>;
+		reset-pin = <&usb_c0_bb_retimer_rst>;
+		ls-en-pin = <&usb_c0_bb_retimer_ls_en>;
+	};
+};
+
+/* typec_1 */
+&i2c_smb_2 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	port_sel = <3>;
+	pinctrl-0 = <&i2c03_scl_gpio010 &i2c03_sda_gpio007>;
+	pinctrl-names = "default";
+
+	tcpc_port1: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+	};
+
+	usb_c1_soc_side_bb_retimer: jhl8040r-c1-soc-side@55 {
+		compatible = "intel,jhl8040r";
+		reg = <0x55>;
+		reset-pin = <&usb_c1_bb_retimer_rst>;
+		ls-en-pin = <&usb_c1_bb_retimer_ls_en>;
+	};
+
+	usb_c1_bb_retimer: jhl8040r-c1@57 {
+		compatible = "intel,jhl8040r";
+		reg = <0x57>;
+		reset-pin = <&usb_c1_bb_retimer_rst>;
+		ls-en-pin = <&usb_c1_bb_retimer_ls_en>;
+	};
+};
+
+/* typec_2 */
+&i2c_smb_3 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	port_sel = <7>;
+	pinctrl-0 = <&i2c07_scl_gpio013 &i2c07_sda_gpio012>;
+	pinctrl-names = "default";
+
+	tcpc_port2: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+	};
+
+	usb_c2_bb_retimer: jhl8040r-c2@58 {
+		compatible = "intel,jhl8040r";
+		reg = <0x58>;
+		reset-pin = <&usb_c2_bb_retimer_rst>;
+		ls-en-pin = <&usb_c2_bb_retimer_ls_en>;
+	};
+};
+
+/* typec_3 */
+&i2c_smb_4 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	port_sel = <2>;
+	pinctrl-0 = <&i2c02_scl_gpio155 &i2c02_sda_gpio154>;
+	pinctrl-names = "default";
+
+	tcpc_port3: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+	};
+
+	usb_c3_bb_retimer: jhl8040r-c3@59 {
+		compatible = "intel,jhl8040r";
+		reg = <0x59>;
+		reset-pin = <&usb_c3_bb_retimer_rst>;
+		ls-en-pin = <&usb_c3_bb_retimer_ls_en>;
+	};
+};
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/bb_retimer.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/bb_retimer.dts
new file mode 100644
index 0000000000..1c760120f1
--- /dev/null
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/bb_retimer.dts
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&i2c_smb_1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	usb_c0_bb_retimer: jhl8040r@56 {
+		compatible = "intel,jhl8040r";
+		reg = <0x56>;
+		label = "USB_C0_BB_RETIMER";
+		reset-pin = <&usb_c0_bb_retimer_rst>;
+	};
+};
+
+&i2c_smb_2 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	usb_c1_bb_retimer: jhl8040r@57 {
+		compatible = "intel,jhl8040r";
+		reg = <0x57>;
+		label = "USB_C1_BB_RETIMER";
+		reset-pin = <&usb_c1_bb_retimer_rst>;
+	};
+};
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/gpio.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/gpio.dts
new file mode 100644
index 0000000000..d526fdcb3b
--- /dev/null
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/gpio.dts
@@ -0,0 +1,299 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_wp;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		all_sys_pwrgd: all-sys-pwrgd {
+			gpios = <&gpio_040_076 15 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
+		}; /* GPIO057 */
+		rsmrst_pwrgd: rsmrst-pwrgd {
+			gpios = <&gpio_200_236 17 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_RSMRST_ODL";
+		}; /* GPIO221 */
+		pch_slp_s0_n: pch-slp-s0-n {
+			gpios = <&gpio_240_276 3 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S0_L";
+		}; /* GPIO243 */
+		vccpdsw_3p3: vccpdsw-3p3 {
+			gpios = <&gpio_200_236 1 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_DSW_PWROK";
+		}; /* GPIO201 */
+		pm_slp_sus_ec_n: pm-slp-sus-ec-n {
+			gpios = <&gpio_200_236 23 GPIO_INPUT>;
+			enum-name = "GPIO_SLP_SUS_L";
+		}; /* GPIO227 */
+		pm_slp_s3_n: pm-slp-s3-n {
+			gpios = <&gpio_140_176 17 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S3_L";
+		}; /* GPIO161 */
+		pm_slp_s4_n: pm-slp-s4-n {
+			gpios = <&gpio_140_176 18 GPIO_INPUT>;
+		}; /* GPIO162 */
+		volume_up {
+			gpios = <&gpio_000_036 30 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		}; /* GPIO036 */
+		vol_dn_ec {
+			gpios = <&gpio_240_276 12 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		}; /* GPIO254 */
+		smc_lid: smc-lid {
+			gpios = <&gpio_200_236 22 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_LID_OPEN";
+		}; /* GPIO226 */
+		mech_pwr_btn_odl: mech-pwr-btn-odl {
+			gpios = <&gpio_100_136 13 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		}; /* GPIO115 */
+		std_adp_prsnt: std-adp-prsnt {
+			gpios = <&gpio_040_076 3 GPIO_INPUT>;
+			enum-name= "GPIO_DC_JACK_PRESENT";
+		}; /* GPIO043 */
+		bc_acok: bc-acok {
+			gpios = <&gpio_140_176 14 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		}; /* GPIO156 */
+		usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 {
+			gpios = <&gpio_140_176 3 GPIO_INPUT>;
+		}; /* GPIO143 */
+		usbc_tcpc_alrt_p1: usbc-tcpc-alrt-p1 {
+			gpios = <&gpio_240_276 1 GPIO_INPUT>;
+		}; /* GPIO241 */
+		usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 {
+			gpios = <&gpio_100_136 24 GPIO_INPUT>;
+		}; /* GPIO130 */
+		usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 {
+			gpios = <&gpio_240_276 2 GPIO_INPUT>;
+		}; /* GPIO242 */
+		usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 {
+			gpios = <&gpio_240_276 0 GPIO_INPUT>;
+		}; /* GPIO240 */
+		usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 {
+			gpios = <&gpio_100_136 1 GPIO_INPUT>;
+		}; /* GPIO101 */
+		usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 {
+			gpios = <&gpio_140_176 4 GPIO_INPUT>;
+		}; /* GPIO144 */
+		usbc_tcpc_ppc_alrt_p3: usbc-tcpc-ppc-alrt-p3 {
+			gpios = <&gpio_140_176 2 GPIO_INPUT>;
+		}; /* GPIO142 */
+		gpio_ec_pch_wake_odl: smc-wake-sci-n-mecc {
+			gpios = <&gpio_040_076 9 GPIO_ODR_HIGH>;
+		}; /* GPIO051 */
+		ec_pch_mkbp_int_odl {
+			gpios = <&gpio_100_136 23 GPIO_ODR_HIGH>;
+		}; /* GPIO127 */
+		lpc_espi_rst_n {
+			gpios = <&gpio_040_076 17 GPIO_INPUT>;
+		}; /* GPIO061 NANA */
+		plt_rst_l {
+			gpios = <&gpio_040_076 10 GPIO_INPUT>;
+		}; /* GPIO052 NANA */
+		slate_mode_indication {
+			gpios = <&gpio_200_236 18 GPIO_INPUT>;
+		}; /* GPIO222 */
+		prochot_ec_n {
+			gpios = <&gpio_000_036 2 GPIO_INPUT>;
+			enum-name = "GPIO_CPU_PROCHOT";
+		}; /* GPIO002 ???? */
+		sys_rst_odl {
+			gpios = <&gpio_040_076 16 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+		}; /* GPIO060 */
+		pm_rsmrst_n {
+			gpios = <&gpio_040_076 12 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_RSMRST_L";
+		}; /* GPIO054 */
+		pm_pwrbtn_n {
+			gpios = <&gpio_000_036 14 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		}; /* GPIO016 */
+		ec_spi_oe_mecc: ec-spi-oe-mecc {
+			gpios = <&gpio_040_076 2 GPIO_OUTPUT_LOW>;
+		}; /* GPIO042 */
+		ec_ds3 {
+			gpios = <&gpio_000_036 21 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP3300_A";
+		}; /* GPIO025 */
+		pch_pwrok_ec {
+			gpios = <&gpio_100_136 6 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_PWROK";
+		}; /* GPIO106 */
+		sys_pwrok {
+			gpios = <&gpio_200_236 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_SYS_PWROK";
+		}; /* GPIO202 */
+		ec_dsw_pwrok {
+			gpios = <&gpio_000_036 28 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_DSW_PWROK";
+		}; /* GPIO034 */
+		gpio_wp: ec-flash-wp-odl {
+			gpios = <&gpio_000_036 12 GPIO_INPUT>;
+		}; /* GPIO014 */
+		ec_h1_packet_mode {
+			gpios = <&gpio_000_036 29 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		}; /* GPIO035 */
+		ec_entering_rw {
+			gpios = <&gpio_100_136 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		}; /* GPIO102 */
+		ccd_mode_odl: ccd-mode-odl {
+			gpios = <&gpio_140_176 29 GPIO_INPUT>;
+			enum-name  = "GPIO_CCD_MODE_ODL";
+		}; /* GPIO175 */
+		bat_det {
+			gpios = <&gpio_200_236 6 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		}; /* GPIO206 */
+		edp_bklt_en_mecc {
+			gpios = <&gpio_000_036 18 GPIO_OUTPUT_HIGH>;
+		}; /* GPIO022 */
+		led_1_l {
+			gpios = <&gpio_140_176 15 GPIO_OUTPUT_HIGH>;
+		}; /* GPIO157 */
+		led_2_l {
+			gpios = <&gpio_140_176 11 GPIO_OUTPUT_HIGH>;
+		}; /* GPIO153 */
+		therm_sen_mecc {
+			gpios = <&gpio_140_176 1 GPIO_OUTPUT_LOW>;
+		}; /* GPIO141 */
+		smb_bs_clk {
+			gpios = <&gpio_000_036 4 GPIO_INPUT>;
+		}; /* GPIO004 */
+		smb_bs_data {
+			gpios = <&gpio_000_036 3 GPIO_INPUT>;
+		}; /* GPIO003 */
+		usbc_tcpc_i2c_clk_p0 {
+			gpios = <&gpio_140_176 0 GPIO_INPUT>;
+		}; /* GPIO140 */
+		usbc_tcpc_i2c_data_p0 {
+			gpios = <&gpio_100_136 26 GPIO_INPUT>;
+		}; /* GPIO132 */
+		usbc_tcpc_i2c_clk_p2 {
+			gpios = <&gpio_000_036 8 GPIO_INPUT>;
+		}; /* GPIO010 */
+		usbc_tcpc_i2c_data_p2 {
+			gpios = <&gpio_000_036 7 GPIO_INPUT>;
+		}; /* GPIO007 */
+		usbc_tcpc_i2c_clk_p1 {
+			gpios = <&gpio_000_036 11 GPIO_INPUT>;
+		}; /* GPIO013 */
+		usbc_tcpc_i2c_data_p1 {
+			gpios = <&gpio_000_036 10 GPIO_INPUT>;
+		}; /* GPIO012 */
+		usbc_tcpc_i2c_clk_p3 {
+			gpios = <&gpio_140_176 13 GPIO_INPUT>;
+		}; /* GPIO155 */
+		usbc_tcpc_i2c_data_p3 {
+			gpios = <&gpio_140_176 12 GPIO_INPUT>;
+		}; /* GPIO154 */
+		sml1_clk_mecc {
+			gpios = <&gpio_100_136 25 GPIO_INPUT>;
+		}; /* GPIO131 */
+		cpu_cat_err_mecc {
+			gpios = <&gpio_000_036 0 GPIO_INPUT>;
+		}; /* GPIO000 */
+		espi_alert0_n {
+			gpios = <&gpio_040_076 19 GPIO_INPUT>;
+		}; /* GPIO063 NANA */
+		batt_disable_ec {
+			gpios = <&gpio_040_076 23 GPIO_INPUT>;
+		}; /* GPIO067 */
+		cpu_c10_gate_mecc {
+			gpios = <&gpio_000_036 19 GPIO_INPUT>;
+		}; /* GPIO023 */
+		smc_sdown_mecc {
+			gpios = <&gpio_240_276 13 GPIO_INPUT>;
+		}; /* GPIO255 */
+		std_adpt_cntrl_gpio {
+			gpios = <&gpio_240_276 4 GPIO_INPUT>;
+		}; /* GPIO244 */
+		smc_onoff_n {
+			gpios = <&gpio_100_136 12 GPIO_INPUT>;
+		}; /* GPIO114 */
+		suswarn {
+			gpios = <&gpio_000_036 20 GPIO_INPUT>;
+		}; /* GPIO024 */
+		me_g3_to_m3_ec {
+			gpios = <&gpio_000_036 27 GPIO_INPUT>;
+		}; /* GPIO033 */
+		gpio_ec_kso_02_inv: ec-kso-02-inv {
+			gpios = <&gpio_040_076 6 (GPIO_OUTPUT_LOW
+				| GPIO_ACTIVE_LOW)>;
+		}; /* GPIO046 */
+
+		usb_c0_bb_retimer_rst: usb-c0-bb-retimer-rst {
+			gpios = <&ioex_c0_port 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_BB_RETIMER_RST";
+		};
+		usb_c0_bb_retimer_ls_en: usb-c0-bb-retimer-ls-en {
+			gpios = <&ioex_c0_port 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_BB_RETIMER_LS_EN";
+		};
+		usb-c0-usb-mux-cntrl-1 {
+			gpios = <&ioex_c0_port 4 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_USB_MUX_CNTRL_1";
+		};
+		usb-c0-usb-mux-cntrl-0 {
+			gpios = <&ioex_c0_port 5 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_USB_MUX_CNTRL_0";
+		};
+		usb_c1_bb_retimer_rst: usb-c1-bb-retimer-rst {
+			gpios = <&ioex_c1_port 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_BB_RETIMER_RST";
+		};
+		usb_c1_bb_retimer_ls_en: usb-c1-bb-retimer-ls-en {
+			gpios = <&ioex_c1_port 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_BB_RETIMER_LS_EN";
+		};
+		usb-c1-hpd {
+			gpios = <&ioex_c1_port 2 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_HPD";
+		};
+		usb-c0-c1-oc {
+			gpios = <&ioex_c1_port 8 GPIO_OUTPUT_HIGH>;
+			enum-name = "IOEX_USB_C0_C1_OC";
+		};
+		usb_c2_bb_retimer_rst: usb-c2-bb-retimer-rst {
+			gpios = <&ioex_c2_port 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C2_BB_RETIMER_RST";
+		};
+		usb_c2_bb_retimer_ls_en: usb-c2-bb-retimer-ls-en {
+			gpios = <&ioex_c2_port 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C2_BB_RETIMER_LS_EN";
+		};
+		usb-c2-usb-mux-cntrl-1 {
+			gpios = <&ioex_c2_port 4 GPIO_OUTPUT_LOW>;
+		};
+		usb-c2-usb-mux-cntrl-0 {
+			gpios = <&ioex_c2_port 5 GPIO_OUTPUT_LOW>;
+		};
+		usb_c3_bb_retimer_rst: usb-c3-bb-retimer-rst {
+			gpios = <&ioex_c3_port 0 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C3_BB_RETIMER_RST";
+		};
+		usb_c3_bb_retimer_ls_en: usb-c3-bb-retimer-ls-en {
+			gpios = <&ioex_c3_port 1 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C3_BB_RETIMER_LS_EN";
+		};
+		usb-c2-c3-oc {
+			gpios = <&ioex_c3_port 8 GPIO_OUTPUT_HIGH>;
+			enum-name = "IOEX_USB_C2_C3_OC";
+		};
+		/* unimplemented GPIOs */
+		en-pp5000 {
+			enum-name = "GPIO_EN_PP5000";
+		};
+	};
+};
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/interrupts.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/interrupts.dts
new file mode 100644
index 0000000000..17986fe2c7
--- /dev/null
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/interrupts.dts
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_lid_open: lid-open {
+			irq-pin = <&smc_lid>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_power_button: power-button {
+			irq-pin = <&mech_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_ac_present: ac-present {
+			irq-pin = <&bc_acok>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_slp_s0: slp-s0 {
+			irq-pin = <&pch_slp_s0_n>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_slp_sus: slp-sus {
+			irq-pin = <&pm_slp_sus_ec_n>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_pg_dsw_pwrok: pg-dsw-pwrok {
+			irq-pin = <&vccpdsw_3p3>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_rsmrst_pwrgd: rsmrst-pwrgd {
+			irq-pin = <&rsmrst_pwrgd>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_all_sys_pwrgd: all-sys-pwrgd {
+			irq-pin = <&all_sys_pwrgd>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 {
+			irq-pin = <&usbc_tcpc_alrt_p0>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usbc_tcpc_alrt_p1: usbc-tcpc-alrt-p1 {
+			irq-pin = <&usbc_tcpc_alrt_p1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 {
+			irq-pin = <&usbc_tcpc_ppc_alrt_p0>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 {
+			irq-pin = <&usbc_tcpc_ppc_alrt_p1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_std_adp_prsnt: std-adp-prsnt {
+			irq-pin = <&std_adp_prsnt>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "board_dc_jack_interrupt";
+		};
+		int_ccd_mode_odl: ccd-mode-odl {
+			irq-pin = <&ccd_mode_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "board_connect_c0_sbu";
+		};
+	};
+};
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/keyboard.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/keyboard.dts
new file mode 100644
index 0000000000..b3577e6afd
--- /dev/null
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/keyboard.dts
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	cros-keyscan {
+		compatible = "cros-keyscan";
+
+		output-settle = <80>;
+		debounce-down = <9000>;
+		debounce-up = <30000>;
+		poll-timeout = <100000>;
+
+		actual-key-mask = <
+			0x14	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xfe	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xca	/* C12 */
+			>;
+	};
+};
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/prj.conf b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/prj.conf
new file mode 100644
index 0000000000..083530c858
--- /dev/null
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/prj.conf
@@ -0,0 +1,84 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_ADLRVP_MCHP=y
+CONFIG_CROS_FLASH_XEC=y
+CONFIG_CROS_SYSTEM_XEC=y
+CONFIG_CROS_KB_RAW_XEC=y
+
+# For MCHP ESPI Drivers
+CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD=y
+CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION=y
+CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE=y
+CONFIG_ESPI_PERIPHERAL_XEC_EMI0=y
+CONFIG_ESPI_PERIPHERAL_ACPI_EC_IBF_EVT_DATA=y
+CONFIG_ESPI_PERIPHERAL_KBC_OBE_CBK=y
+CONFIG_ESPI_PERIPHERAL_KBC_IBF_EVT_DATA=y
+
+# Invoke SoC Python script to create zephyr.mchp.bin which
+# is zephyr.bin processed for Boot-ROM loading.
+CONFIG_MCHP_MEC_UNSIGNED_HEADER=y
+CONFIG_MCHP_MEC_HEADER_FLASH_SIZE_256K=y
+
+# Support Zephyr SPI NOR driver to work with MCHP SPI driver
+CONFIG_SPI_NOR=y
+CONFIG_SPI_XEC_QMSPI_FULL_DUPLEX=y
+
+# Sensors - MCHP TACH driver under sensor
+CONFIG_SENSOR=n
+CONFIG_SENSOR_SHELL=n
+
+# Debug option
+# Enable flash console commands
+CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y
+
+
+## TODO - support following features next
+# Fan
+CONFIG_PLATFORM_EC_FAN=n
+
+# RTC
+CONFIG_PLATFORM_EC_RTC=n
+
+# PWM
+CONFIG_PWM=n
+CONFIG_PWM_SHELL=n
+
+## INTEL RVP
+# Host command
+CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET=n
+
+# Power Sequencing
+CONFIG_PLATFORM_EC_THROTTLE_AP=n
+
+## ADL RVP
+# CBI
+CONFIG_EEPROM=n
+CONFIG_EEPROM_AT24=n
+CONFIG_EEPROM_SHELL=n
+CONFIG_PLATFORM_EC_CBI_EEPROM=n
+
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=n
+CONFIG_PLATFORM_EC_LED_PWM=n
+CONFIG_PLATFORM_EC_LED_PWM_TASK_DISABLED=n
+
+# Temperature sensors
+CONFIG_PLATFORM_EC_TEMP_SENSOR=n
+CONFIG_PLATFORM_EC_THERMISTOR=n
+CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=n
+
+# Charger
+CONFIG_PLATFORM_EC_DEDICATED_CHARGE_PORT=y
+
+# H1 issues second reset
+CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=n
+
+# 7-Segment Display
+CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY=n
+
+# Debug options
+# Enable flash console commands
+CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y
+CONFIG_WDT_DISABLE_AT_BOOT=y
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/usbc.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/usbc.dts
new file mode 100644
index 0000000000..471a1f52e9
--- /dev/null
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/usbc.dts
@@ -0,0 +1,89 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			usb_mux_chain_0: usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c0_bb_retimer
+					     &virtual_mux_c0>;
+			};
+			usb_mux_alt_chain_0: usb-mux-alt-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&usb_c0_bb_retimer
+					     &usb_c0_soc_side_bb_retimer
+					     &virtual_mux_c0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_c0: virtual-mux-c0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			tcpc = <&tcpc_port1>;
+			usb_mux_chain_1: usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c1_bb_retimer
+					     &virtual_mux_c1>;
+			};
+			usb_mux_alt_chain_1: usb-mux-alt-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&usb_c1_bb_retimer
+					     &usb_c1_soc_side_bb_retimer
+					     &virtual_mux_c1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_c1: virtual-mux-c1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port2@2 {
+			compatible = "named-usbc-port";
+			reg = <2>;
+			tcpc = <&tcpc_port2>;
+			usb_mux_chain_2: usb-mux-chain-2 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c2_bb_retimer
+					     &virtual_mux_c2>;
+			};
+		};
+		port2-muxes {
+			virtual_mux_c2: virtual-mux-c2 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port3@3 {
+			compatible = "named-usbc-port";
+			reg = <3>;
+			tcpc = <&tcpc_port3>;
+			usb_mux_chain_3: usb-mux-chain-3 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c3_bb_retimer
+					     &virtual_mux_c3>;
+			};
+		};
+		port3-muxes {
+			virtual_mux_c3: virtual-mux-c3 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};