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| author | Alexandru M Stan <amstan@chromium.org> | 2014-12-16 14:47:32 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-12-17 02:18:16 +0000 |
| commit | 3b101e56a9e058aee19933f9adfae1c8bb2dbedd (patch) | |
| tree | c8632f131f88b622d334651f063bc58f799f9228 | |
| parent | 3c0d9166cf1b1aa35152d3757fbd0566a9cbe6d5 (diff) | |
| download | chrome-ec-3b101e56a9e058aee19933f9adfae1c8bb2dbedd.tar.gz | |
NVIC: Adjust priority setting
Cortex-m0 we supports 2 bit priorities for the NVIC, yet we clear with 0x7 (3
bits). Change so we now clear with 0x3
Also limited priority to the max available (so we don't set extra bits we don't
want or modulus the priority, otherwise setting priority 8 will actual give you
priority 0) in both cortex-m and cortex-m0.
BUG=None, discovered while looking at the code
TEST=Should be no functional change, NVIC priorities should still work the same.
BRANCH=None
Change-Id: I31ba041449cae96983753b297e2631c310a406c4
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236086
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
| -rw-r--r-- | core/cortex-m/task.c | 2 | ||||
| -rw-r--r-- | core/cortex-m0/task.c | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index 7f667b3f4a..b90f91ce00 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -453,6 +453,8 @@ static void __nvic_init_irqs(void) uint8_t irq = __irqprio[i].irq; uint8_t prio = __irqprio[i].priority; uint32_t prio_shift = irq % 4 * 8 + 5; + if (prio > 0x7) + prio = 0x7; CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(0x7 << prio_shift)) | diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c index af3a4e2277..4e9c66ee95 100644 --- a/core/cortex-m0/task.c +++ b/core/cortex-m0/task.c @@ -431,9 +431,11 @@ static void __nvic_init_irqs(void) uint8_t irq = __irqprio[i].irq; uint8_t prio = __irqprio[i].priority; uint32_t prio_shift = irq % 4 * 8 + 6; + if (prio > 0x3) + prio = 0x3; CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & - ~(0x7 << prio_shift)) | + ~(0x3 << prio_shift)) | (prio << prio_shift); } } |