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| author | Dino Li <Dino.Li@ite.com.tw> | 2021-09-02 15:21:46 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-09-03 06:25:23 +0000 |
| commit | 055d4fa18627c0d9e5a26285d7be44297e9f4722 (patch) | |
| tree | ab1593bd0b84b1fac445469c416406329af27278 | |
| parent | 8e75e2594bfa0b902f2c032e7036c59050ec6e2d (diff) | |
| download | chrome-ec-055d4fa18627c0d9e5a26285d7be44297e9f4722.tar.gz | |
it83xx/riscv: Ensure IER has been disabled before enabling CPU interrupt
This CL read EC's IER one time after configured. The load operation
will ensure chip-level's interrupt has been disabled before enabling
CPU interrupt.
BRANCH=asurada, icarus
BUG=b:179206540
TEST=create stress test on it8xxx2 evb:
- Loop calling task_disable_irq() and task_enable_irq() to
enable and disable IRQ 13 (keyboard KSI interrupt).
- Toggle KSI continuously.
Without the patch, EC will hit IRQ 0 issue in two seconds.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I56bad182bd101d45b00368083b60aabbd9fb8bdb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3139652
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
(cherry picked from commit 7999cc115b95dc918ec6a89d4e0f4b55728557d7)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3139520
Tested-by: Eric Yilun Lin <yllin@google.com>
Auto-Submit: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
| -rw-r--r-- | chip/it83xx/irq.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c index 76ae66a123..5500c2face 100644 --- a/chip/it83xx/irq.c +++ b/chip/it83xx/irq.c @@ -126,8 +126,16 @@ void chip_disable_irq(int irq) int bit = irq % 8; /* SOC's interrupts share CPU machine-mode external interrupt */ - if (IS_ENABLED(CHIP_CORE_RISCV)) + if (IS_ENABLED(CHIP_CORE_RISCV)) { + volatile uint8_t _ier __unused; + IT83XX_INTC_REG(irq_groups[group].ier_off) &= ~BIT(bit); + /* + * This load operation will guarantee the above modification of + * EC's register can be seen by any following instructions. + */ + _ier = IT83XX_INTC_REG(irq_groups[group].ier_off); + } /* SOC's interrupts use CPU HW interrupt 2 ~ 15 */ if (IS_ENABLED(CHIP_CORE_NDS32)) |