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| author | Dino Li <Dino.Li@ite.com.tw> | 2022-05-31 15:47:56 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-06-10 05:51:13 +0000 |
| commit | 43127525f922b768d93c6abe509a4b072746993f (patch) | |
| tree | 854c1776c94c09b33b656c892cf54c2910aa58f9 | |
| parent | 3b3986ce8de723d38d07bfc06612d827c6ec2e55 (diff) | |
| download | chrome-ec-43127525f922b768d93c6abe509a4b072746993f.tar.gz | |
config: riscv: add CONFIG_RISCV_EXTENSION_M configuration
This makes the 'M' extension to be configurable.
BUG=b:235297478
BRANCH=asurada,cherry,icarus
TEST=- buildall
- ISA for cherry images includes "M" extension (-march=rv32imac)
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I56957a6767378121443659a170ca33896ada67ce
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3690041
Reviewed-by: Eric Yilun Lin <yllin@google.com>
(cherry picked from commit adae86b9387e261919d5e9921814f0d8f31f49fa)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3695855
Commit-Queue: Eric Yilun Lin <yllin@google.com>
| -rw-r--r-- | core/riscv-rv32i/build.mk | 5 | ||||
| -rw-r--r-- | include/config.h | 6 | ||||
| -rw-r--r-- | util/config_allowed.txt | 1 |
3 files changed, 11 insertions, 1 deletions
diff --git a/core/riscv-rv32i/build.mk b/core/riscv-rv32i/build.mk index 34f059e70c..376bd2c093 100644 --- a/core/riscv-rv32i/build.mk +++ b/core/riscv-rv32i/build.mk @@ -12,8 +12,11 @@ $(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\ # Enable FPU extension if config option of FPU is enabled. _FPU_EXTENSION=$(if $(CONFIG_FPU),f,) +# Enable the 'M' extension if config option of RISCV_EXTENSION_M is enabled. +_M_EXTENSION=$(if $(CONFIG_RISCV_EXTENSION_M),m,) # CPU specific compilation flags -CFLAGS_CPU+=-march=rv32ima$(_FPU_EXTENSION)c -mabi=ilp32$(_FPU_EXTENSION) -Os +CFLAGS_CPU+=-march=rv32i$(_M_EXTENSION)a$(_FPU_EXTENSION)c +CFLAGS_CPU+=-mabi=ilp32$(_FPU_EXTENSION) -Os # RISC-V does not trap division by zero, enable the sanitizer to check those. # With `-fsanitize-undefined-trap-on-error`, we lose a bit of specificity on the # exact issue, but the added code is as small as it gets. diff --git a/include/config.h b/include/config.h index f2de323ca8..244ab4c57c 100644 --- a/include/config.h +++ b/include/config.h @@ -2833,6 +2833,12 @@ #undef CONFIG_IT83XX_VCC_3P3V /* + * Support the standard integer multiplication and division instruction + * extension. + */ +#define CONFIG_RISCV_EXTENSION_M + +/* * If this is not defined, the firmware will revert the JTAG selection * triggered by the hardware strap pin. * Un-define this flag by default for all real platforms. see (b/129908668) diff --git a/util/config_allowed.txt b/util/config_allowed.txt index e7e751116c..90648e81b5 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -753,6 +753,7 @@ CONFIG_RAM_BASE CONFIG_RAM_SIZE CONFIG_REGULATOR_IR357X CONFIG_RESTRICTED_CONSOLE_COMMANDS +CONFIG_RISCV_EXTENSION_M CONFIG_RMA_AUTH CONFIG_RMA_AUTH_USE_P256 CONFIG_RNG |