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| author | Kyoung Kim <kyoung.il.kim@intel.com> | 2015-07-23 10:49:47 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-28 18:53:32 +0000 |
| commit | 4ff95401b5ba8dd51dff7d87878138db19c806d4 (patch) | |
| tree | 073ba134f352a5c1ed46c5e617cd3409ab4af030 | |
| parent | 6eecf91b63af56209acf3ae367ab28bcc3fceb1e (diff) | |
| download | chrome-ec-4ff95401b5ba8dd51dff7d87878138db19c806d4.tar.gz | |
mec1322: Power state transition in case of apshutdown
In case of 'apshutdown', SOC loses power immediately
while EC is waiting for SOC's PMC_SUSPWRDNACK signal
forever.
BUG=chrome-os-partner:43038
TEST=Cyan
BRANCH=none
Change-Id: I34321d00a89011e90222ea5916a42e9a51d4f4b0
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/288203
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
| -rw-r--r-- | power/braswell.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/power/braswell.c b/power/braswell.c index 826ae7ab5a..50f6c5cbf1 100644 --- a/power/braswell.c +++ b/power/braswell.c @@ -51,6 +51,7 @@ #define IN_ALL_S0 (IN_PGOOD_S0 | IN_ALL_PM_SLP_DEASSERTED) static int throttle_cpu; /* Throttle CPU? */ +static int forcing_shutdown; /* Forced shutdown in progress? */ void chipset_force_shutdown(void) { @@ -62,6 +63,7 @@ void chipset_force_shutdown(void) */ gpio_set_level(GPIO_PCH_SYS_PWROK, 0); gpio_set_level(GPIO_PCH_RSMRST_L, 0); + forcing_shutdown = 1; } void chipset_reset(int cold_reset) @@ -279,6 +281,25 @@ enum power_state power_handle_state(enum power_state state) return power_get_pause_in_s5() ? POWER_S5 : POWER_S5G3; case POWER_S5G3: + /* + * in case shutdown is already done by apshutdown + * (or chipset_force_shutdown()), SOC already lost + * power and can't assert PMC_SUSPWRDNACK any more. + */ + if (forcing_shutdown) { + /* Config pins for SOC G3 */ + gpio_config_module(MODULE_GPIO, 1); +#ifndef CONFIG_PMIC + gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1); +#endif + + forcing_shutdown = 0; + + CPRINTS("Enter SOC G3"); + + return POWER_G3; + } + if (gpio_get_level(GPIO_PCH_SUSPWRDNACK) == 1) { /* Assert RSMRST# */ gpio_set_level(GPIO_PCH_RSMRST_L, 0); |