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| author | Mary Ruthven <mruthven@chromium.org> | 2021-08-27 18:32:23 +0000 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-09-07 19:44:15 +0000 |
| commit | 5106abe1e3d5eff0f64c9c71243bf75d1f2fc876 (patch) | |
| tree | 69ecbb807d55bfedf7b189161db9496bdf12e34b | |
| parent | 203ad16b4d6fc746c9d199d14fdfb494f349474f (diff) | |
| download | chrome-ec-5106abe1e3d5eff0f64c9c71243bf75d1f2fc876.tar.gz | |
Revert "cr50: switch SPI CS to GPIO mode"
This reverts commit b3480c1ae2ef6dcc246cfa39c1d8daeee715da21.
Reason for revert: Recent CCD changes cause flash ap issues on eve
Original change's description:
> cr50: switch SPI CS to GPIO mode
>
> To be able to send and receive multiple SPI buffer quantities in a
> single SPI transaction it is necessary to control the SPI CS signal
> directly, as opposed to connecting it to the SPI controller.
>
> Direct mode allows to keep CS asserted as long as necessary to
> transfer the full data blob, size of which might exceed the the size
> of the SPI controller buffer.
>
> BUG=b:79492818
> TEST=flashrom access still works fine:
>
> $ flashrom -p raiden_debug_spi:target=ap --flash-name
> flashrom f10dff7b-dirty on Linux 5.4.0-71-generic (x86_64)
> flashrom is free software, get the source code at https://flashrom.org
>
> Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
> Raiden target: 2
> Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, SPI) on...
> vendor="GigaDevice" name="GD25Q127C/GD25Q128C"
>
> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
> Change-Id: Idecf019d3fd19675d7f78e4dc1140106a2112c6b
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2973580
> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
> (cherry picked from commit c6095192742c9f59f72a6178ece5a2dd8cea4e43)
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004085
> Reviewed-by: Andrey Pronin <apronin@chromium.org>
> Tested-by: Mary Ruthven <mruthven@chromium.org>
> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
Bug: b:79492818
Change-Id: Icc1498ee7bc6ff6333b639d120dc8a7d4b6b6980
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3124573
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Mary Ruthven <mruthven@chromium.org>
(cherry picked from commit f83c0cd189088cb849b8a58b688c2bbee45606c2)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3142860
| -rw-r--r-- | board/cr50/board.c | 5 | ||||
| -rw-r--r-- | board/cr50/board.h | 1 | ||||
| -rw-r--r-- | board/cr50/usb_spi.c | 3 |
3 files changed, 7 insertions, 2 deletions
diff --git a/board/cr50/board.c b/board/cr50/board.c index 0e2e5edfef..d7e9742291 100644 --- a/board/cr50/board.c +++ b/board/cr50/board.c @@ -992,8 +992,9 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); #endif /* SPI devices */ -const struct spi_device_t spi_devices[] = { [CONFIG_SPI_FLASH_PORT] = { - 0, 2, GPIO_SPI_CS_L } }; +const struct spi_device_t spi_devices[] = { + [CONFIG_SPI_FLASH_PORT] = {0, 2, GPIO_COUNT} +}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); int flash_regions_to_enable(struct g_flash_region *regions, diff --git a/board/cr50/board.h b/board/cr50/board.h index 9be61d9703..25d0ea5396 100644 --- a/board/cr50/board.h +++ b/board/cr50/board.h @@ -132,6 +132,7 @@ /* Enable SPI controller (SPI) module */ #define CONFIG_SPI_CONTROLLER +#define CONFIG_SPI_CONTROLLER_NO_CS_GPIOS #define CONFIG_SPI_CONTROLLER_CONFIGURE_GPIOS #define CONFIG_SPI_FLASH_PORT 0 diff --git a/board/cr50/usb_spi.c b/board/cr50/usb_spi.c index ac294546d9..47c1a070e7 100644 --- a/board/cr50/usb_spi.c +++ b/board/cr50/usb_spi.c @@ -223,6 +223,7 @@ static void enable_spi_pinmux(void) /* Connect DIO A4, A8, and A14 to the SPI peripheral */ GWRITE(PINMUX, DIOA4_SEL, 0); /* SPI_MOSI */ GWRITE(PINMUX, DIOA8_SEL, 0); /* SPI_CS_L */ + GWRITE(PINMUX, DIOA14_SEL, 0); /* SPI_CLK */ /* Set SPI_CS to be an internal pull up */ GWRITE_FIELD(PINMUX, DIOA14_CTL, PU, 1); @@ -251,6 +252,7 @@ static void disable_spi_pinmux(void) /* TODO: Implement way to get the gpio */ ASSERT(GREAD(PINMUX, GPIO0_GPIO7_SEL) == GC_PINMUX_DIOA4_SEL); ASSERT(GREAD(PINMUX, GPIO0_GPIO8_SEL) == GC_PINMUX_DIOA8_SEL); + ASSERT(GREAD(PINMUX, GPIO0_GPIO9_SEL) == GC_PINMUX_DIOA14_SEL); GWRITE_FIELD(PINMUX, DIOA4_CTL, PD, 1); /* SPI_MOSI */ GWRITE_FIELD(PINMUX, DIOA8_CTL, PD, 1); /* SPI_CLK */ @@ -258,6 +260,7 @@ static void disable_spi_pinmux(void) /* Set SPI MOSI, CLK, and CS_L as inputs */ GWRITE(PINMUX, DIOA4_SEL, GC_PINMUX_GPIO0_GPIO7_SEL); GWRITE(PINMUX, DIOA8_SEL, GC_PINMUX_GPIO0_GPIO8_SEL); + GWRITE(PINMUX, DIOA14_SEL, GC_PINMUX_GPIO0_GPIO9_SEL); } /*****************************************************************************/ |