diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2020-05-08 09:22:44 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-05-08 17:06:07 +0000 |
| commit | f9e5a32fb99bb686f247a0e2d9d2f1ec2c0e576f (patch) | |
| tree | 49d182fcae51c13031b09d4a5f85b9fea659f0af | |
| parent | 159d9723de232e3bd9d428289db507b0f37beb79 (diff) | |
| download | chrome-ec-f9e5a32fb99bb686f247a0e2d9d2f1ec2c0e576f.tar.gz | |
step back to 0.3.26 state
The MP branch got ahead of itself, we need to publish an intermediate
release before 5.4. Let's bring the branch back to 0.3.26 state so
changes necessary for the intermediate release can be made cleanly.
Once the release is cut, this patch will be reverted to bring the
branch back to the top.
BRANCH=none
BUG=none
TEST='git diff 831c53f' returns no output.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: If47166b97d1f0faf1c315982827e2c2d5ce00c78
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2190814
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
58 files changed, 919 insertions, 2075 deletions
diff --git a/Makefile.rules b/Makefile.rules index 0453cbc5d0..ce564aa455 100644 --- a/Makefile.rules +++ b/Makefile.rules @@ -411,9 +411,7 @@ $(out)/RW/%.o:%.S # Conditionally force the rebuilding of ec_version.h only if it would be # changed. old_version_hash := $(shell cat $(out)/ec_version.h 2> /dev/null | md5sum -) -new_version_hash := $(shell BOARD=$(BOARD) CR50_DEV=$(CR50_DEV) \ - CR50_SQA=$(CR50_SQA) CRYPTO_TEST=$(CRYPTO_TEST) \ - ./util/getversion.sh | md5sum -) +new_version_hash := $(shell BOARD=$(BOARD) ./util/getversion.sh | md5sum -) ifneq ($(old_version_hash),$(new_version_hash)) .PHONY: $(out)/ec_version.h diff --git a/PRESUBMIT.cfg b/PRESUBMIT.cfg index f1090a84a1..57b98a6b1a 100644 --- a/PRESUBMIT.cfg +++ b/PRESUBMIT.cfg @@ -1,4 +1,5 @@ [Hook Overrides] +branch_check: true checkpatch_check: true # We are using Linux style indentation with tabs diff --git a/board/cr50/board.c b/board/cr50/board.c index 3456d5eaf5..86643dd4be 100644 --- a/board/cr50/board.c +++ b/board/cr50/board.c @@ -9,7 +9,6 @@ #include "common.h" #include "console.h" #include "dcrypto/dcrypto.h" -#include "ec_comm.h" #include "ec_version.h" #include "endian.h" #include "extension.h" @@ -461,18 +460,12 @@ static void init_ac_detect(void) /*****************************************************************************/ /* - * There's no way to have more than one trigger condition on a GPIO, - * so force a compiler error if we try. The workaround is to use the pinmux to - * connect as many GPIOs as the number of required trigger conditions to the - * same input and configure each one for a separate condition. - */ -#define GPIO_INT_COND(x) ((x) & GPIO_INT_ANY & ~GPIO_INPUT) -/* - * Checks flags has only one bit set among GPIO_INT_F_RISING, - * GPIO_INT_F_FALLING, GPIO_INT_F_LOW, GPIO_INT_F_HIGH. + * There's no way to trigger on both rising and falling edges, so force a + * compiler error if we try. The workaround is to use the pinmux to connect + * two GPIOs to the same input and configure each one for a separate edge. */ #define GPIO_INT(name, pin, flags, signal) \ - BUILD_ASSERT((GPIO_INT_COND(flags) & (GPIO_INT_COND(flags) - 1)) == 0); + BUILD_ASSERT(((flags) & GPIO_INT_BOTH) != GPIO_INT_BOTH); #include "gpio.wrap" /** @@ -577,10 +570,9 @@ void board_configure_deep_sleep_wakepins(void) * not being used and reenable them in their init functions on * resume. */ - gpio_set_wakepin(GPIO_STRAP_B1, 0); /* SPS_CS_L */ - gpio_set_wakepin(GPIO_STRAP_A0, 0); /* I2CS_SDA */ - gpio_set_wakepin(GPIO_STRAP_A1, 0); /* I2CS_SCL */ - + GWRITE_FIELD(PINMUX, EXITEN0, DIOA12, 0); /* SPS_CS_L */ + GWRITE_FIELD(PINMUX, EXITEN0, DIOA1, 0); /* I2CS_SDA */ + GWRITE_FIELD(PINMUX, EXITEN0, DIOA9, 0); /* I2CS_SCL */ /* Remove the pulldown on EC uart tx and disable the input */ GWRITE_FIELD(PINMUX, DIOB5_CTL, PD, 0); @@ -596,16 +588,25 @@ void board_configure_deep_sleep_wakepins(void) * resuming from deep sleep the TPM will be reset. Cr50 doesn't need to * read the low value and then reset. */ - - /* - * Configure plt_rst_l (DIOM3) or sys_rst_(DIOM0) to wake on high. - * Note: the pinmux with GPIO_TPM_RST_L is configured in - * configure_board_specific_gpios(). - */ - gpio_set_wakepin(GPIO_TPM_RST_L, GPIO_HIB_WAKE_HIGH); - - if (board_has_ec_cr50_comm_support()) - gpio_set_wakepin(GPIO_EC_PACKET_MODE_EN, GPIO_HIB_WAKE_HIGH); + if (board_use_plt_rst()) { + /* Configure plt_rst_l to wake on high */ + /* Disable plt_rst_l as a wake pin */ + GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 0); + /* Reconfigure the pin */ + GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM3, 0); /* level sensitive */ + GWRITE_FIELD(PINMUX, EXITINV0, DIOM3, 0); /* wake on high */ + /* enable powerdown exit */ + GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 1); + } else { + /* Configure plt_rst_l to wake on high */ + /* Disable sys_rst_l as a wake pin */ + GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 0); + /* Reconfigure the pin */ + GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM0, 0); /* level sensitive */ + GWRITE_FIELD(PINMUX, EXITINV0, DIOM0, 0); /* wake on high */ + /* enable powerdown exit */ + GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 1); + } } static void deferred_tpm_rst_isr(void); @@ -637,6 +638,22 @@ static void configure_board_specific_gpios(void) /* Enable the input */ GWRITE_FIELD(PINMUX, DIOM3_CTL, IE, 1); + + /* + * Make plt_rst_l routed to DIOM3 a low level sensitive wake + * source. This way when a plt_rst_l pulse comes along while + * H1 is in sleep, the H1 wakes from sleep first, enabling all + * necessary clocks, and becomes ready to generate an + * interrupt on the rising edge of plt_rst_l. + * + * It takes at most 150 us to wake up, and the pulse is at + * least 1ms long. + */ + GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM3, 0); + GWRITE_FIELD(PINMUX, EXITINV0, DIOM3, 1); + + /* Enable powerdown exit on DIOM3 */ + GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 1); } else { /* Use sys_rst_l as the tpm reset signal. */ /* Select for TPM_RST_L */ @@ -645,19 +662,14 @@ static void configure_board_specific_gpios(void) GWRITE(PINMUX, GPIO1_GPIO4_SEL, GC_PINMUX_DIOM0_SEL); /* Enable the input */ GWRITE_FIELD(PINMUX, DIOM0_CTL, IE, 1); - } - /* - * Now that TPM_RST_L has been connected to the right signal, enable it - * as wake_low. This way when a tpm_rst_l pulse comes along while H1 is - * in sleep, the H1 wakes from sleep first, enabling all necessary - * clocks, and becomes ready to generate an interrupt on the rising edge - * of tpm_rst_l. - * - * It takes at most 150 us to wake up, and the pulse is at - * least 1ms long. - */ - gpio_set_wakepin(GPIO_TPM_RST_L, GPIO_HIB_WAKE_LOW); + /* Set to be level sensitive */ + GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM0, 0); + /* wake on low */ + GWRITE_FIELD(PINMUX, EXITINV0, DIOM0, 1); + /* Enable powerdown exit on DIOM0 */ + GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 1); + } /* Connect the correct pin to the lid open/recovery switch gpio. */ switch (board_get_ccd_rec_lid_pin()) { case BOARD_CCD_REC_LID_PIN_DIOA1: @@ -692,21 +704,16 @@ static void configure_board_specific_gpios(void) GWRITE(PINMUX, DIOB4_SEL, GC_PINMUX_GPIO0_GPIO2_SEL); GWRITE(PINMUX, GPIO0_GPIO2_SEL, GC_PINMUX_DIOB4_SEL); - /* Enable the input for DIOB4 */ + /* Enable the input */ GWRITE_FIELD(PINMUX, DIOB4_CTL, IE, 1); - - /* Connect GPIO_EC_PACKET_MODE_EN to DIOB3 as input. */ - GWRITE(PINMUX, GPIO1_GPIO7_SEL, GC_PINMUX_DIOB3_SEL); - /* Connect GPIO_EC_PACKET_MODE_DIS to DIOB3 as input. */ - GWRITE(PINMUX, GPIO1_GPIO8_SEL, GC_PINMUX_DIOB3_SEL); } else { /* Connect GPIO_AP_FLASH_SELECT to DIOB3. */ GWRITE(PINMUX, DIOB3_SEL, GC_PINMUX_GPIO0_GPIO2_SEL); GWRITE(PINMUX, GPIO0_GPIO2_SEL, GC_PINMUX_DIOB3_SEL); - } - /* Enable the input for DIOB3 */ - GWRITE_FIELD(PINMUX, DIOB3_CTL, IE, 1); + /* Enable the input */ + GWRITE_FIELD(PINMUX, DIOB3_CTL, IE, 1); + } } static uint8_t mismatched_board_id; @@ -857,7 +864,7 @@ static void board_init(void) * HOOK_INIT, not at +1.0 seconds. */ } -DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_CR50_BOARD); +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /** * Hook for CCD config loaded/changed. @@ -1046,12 +1053,6 @@ void board_reboot_ec(void) } DECLARE_DEFERRED(board_reboot_ec); -void board_reboot_ec_deferred(int32_t usec_delay) -{ - if (usec_delay >= 0) - hook_call_deferred(&board_reboot_ec_data, usec_delay); -} - /* * This interrupt handler will be called if the RBOX key combo is detected. */ @@ -1148,8 +1149,6 @@ void assert_ec_rst(void) /* Prevent bit bang interrupt storm. */ if (uart_bitbang_is_enabled()) task_disable_irq(bitbang_config.rx_irq); - else if (board_has_ec_cr50_comm_support()) - ec_efs_reset(); wait_ec_rst(1); @@ -1523,10 +1522,15 @@ void i2cs_set_pinmux(void) */ GWRITE(PINMUX, GPIO0_GPIO14_SEL, GC_PINMUX_DIOA1_SEL); - /* Configure the I2CS_SDA signal, DIOA1, as wake falling */ - gpio_set_wakepin(GPIO_STRAP_A0, GPIO_HIB_WAKE_FALLING); - /* Configure the I2CS_SCL signal, DIOA9, as wake falling */ - gpio_set_wakepin(GPIO_STRAP_A1, GPIO_HIB_WAKE_FALLING); + /* Allow I2CS_SCL to wake from sleep */ + GWRITE_FIELD(PINMUX, EXITEDGE0, DIOA9, 1); /* edge sensitive */ + GWRITE_FIELD(PINMUX, EXITINV0, DIOA9, 1); /* wake on low */ + GWRITE_FIELD(PINMUX, EXITEN0, DIOA9, 1); /* enable powerdown exit */ + + /* Allow I2CS_SDA to wake from sleep */ + GWRITE_FIELD(PINMUX, EXITEDGE0, DIOA1, 1); /* edge sensitive */ + GWRITE_FIELD(PINMUX, EXITINV0, DIOA1, 1); /* wake on low */ + GWRITE_FIELD(PINMUX, EXITEN0, DIOA1, 1); /* enable powerdown exit */ } static int command_sysinfo(int argc, char **argv) diff --git a/board/cr50/board.h b/board/cr50/board.h index b8298ce2eb..b13931607f 100644 --- a/board/cr50/board.h +++ b/board/cr50/board.h @@ -336,12 +336,6 @@ int board_fwmp_allows_unlock(void); int board_vboot_dev_mode_enabled(void); void board_reboot_ap(void); void board_reboot_ec(void); -/** - * Reboot the EC - * @param usec_delay microseconds to delay in rebooting EC. - * negative input shall be disregarded. - */ -void board_reboot_ec_deferred(int usec_delay); void board_closed_loop_reset(void); int board_wipe_tpm(int reset_required); int board_is_first_factory_boot(void); @@ -406,7 +400,6 @@ int board_in_prod_mode(void); #define UART_CR50 0 #define UART_AP 1 #define UART_EC 2 -#define UART_NULL 0xff #define UARTN UART_CR50 @@ -444,8 +437,6 @@ enum nvmem_users { #define CONFIG_FACTORY_MODE #define CONFIG_RNG -#define CONFIG_EC_EFS_SUPPORT - #define CONFIG_ENABLE_H1_ALERTS /* Enable hardware backed brute force resistance feature */ diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc index 9051d422a3..b74119d4b7 100644 --- a/board/cr50/gpio.inc +++ b/board/cr50/gpio.inc @@ -50,7 +50,6 @@ * GPIO0.0 int_ap_l * GPIO0.1 ec_flash_select * GPIO0.2 ap_flash_select - * GPIO0.3 DIOM4 used for physical presence * GPIO0.4 sys_rst_l_out * GPIO0.5 ccd_mode_l * GPIO0.6 batt_pres_l @@ -70,8 +69,6 @@ * GPIO1.4 detect_tpm_rst_asserted * GPIO1.5 unwedge_i2cs_scl * GPIO1.6 monitor_i2cs_sda - * GPIO1.7 ec_packet_mode_en - * GPIO1.8 ec_packet_mode_dis * GPIO1.10 rec_lid_switch * GPIO1.11 ec_tx_cr50_rx_in * GPIO1.12 strap_a0 @@ -109,15 +106,6 @@ GPIO_INT(DETECT_SERVO, PIN(1, 3), GPIO_INT_HIGH | GPIO_PULL_DOWN, GPIO_INT(DETECT_TPM_RST_L_ASSERTED, PIN(1, 4), GPIO_INT_FALLING, tpm_rst_asserted) -/* - * These GPIOs are to enable or disable EC-CR50 communication. - * NOTE: If these are changed, you must update the information in board.c - * and ec_comm.c - */ -GPIO_INT(EC_PACKET_MODE_EN, PIN(1, 7), GPIO_INT_RISING, ec_comm_packet_mode_en) -GPIO_INT(EC_PACKET_MODE_DIS, PIN(1, 8), GPIO_INT_FALLING, - ec_comm_packet_mode_dis) - /*****************************************************************************/ /* NON STANDARD INTERRUPT GPIOs - handlers defined and configured in board.c */ /* @@ -163,12 +151,6 @@ GPIO(SPI_MOSI, PIN(0, 7), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(SPI_CLK, PIN(0, 8), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(SPI_CS_L, PIN(0, 9), GPIO_INPUT) -/* - * Generic pulled up input used for physical presence indication on some - * devices. - */ -GPIO(DIOM4, PIN(0, 3), GPIO_INPUT) - /* Used during *chip* factory process. */ GPIO(DIOB4, PIN(0, 10), GPIO_INPUT | GPIO_PULL_DOWN) @@ -238,9 +220,6 @@ UNIMPLEMENTED(ENTERING_RW) /* GPIOs - mark outputs as inputs too, to read back from the driven pad */ PINMUX(GPIO(INT_AP_L), A5, DIO_INPUT) - -PINMUX(GPIO(DIOM4), M4, DIO_INPUT | GPIO_PULL_UP) - PINMUX(GPIO(EC_FLASH_SELECT), B2, DIO_INPUT) PINMUX(GPIO(MONITOR_I2CS_SDA), A1, GPIO_INPUT) diff --git a/board/cr50/rdd.c b/board/cr50/rdd.c index 228f076831..2d1403ec02 100644 --- a/board/cr50/rdd.c +++ b/board/cr50/rdd.c @@ -6,7 +6,6 @@ #include "case_closed_debug.h" /* For ccd_ext_is_enabled() */ #include "ccd_config.h" #include "console.h" -#include "ec_comm.h" #include "gpio.h" #include "hooks.h" #include "i2c.h" @@ -16,7 +15,6 @@ #include "system.h" #include "uart_bitbang.h" #include "uartn.h" -#include "usart.h" #include "usb_api.h" #include "usb_console.h" #include "usb_i2c.h" @@ -56,13 +54,7 @@ enum ccd_block_flags { * uart while servo is connected, it could break the hardware and the * ccd uart could become permanently unusable. */ - CCD_BLOCK_IGNORE_SERVO = BIT(3), - - /* - * This will block EC-CR50-communication. CR50 should not enable EC - * UART. - */ - CCD_BLOCK_EC_CR50_COMM = BIT(4) + CCD_BLOCK_IGNORE_SERVO = BIT(3) }; /* Which UARTs are blocked by console command */ @@ -86,32 +78,60 @@ int uart_tx_is_connected(int uart) return !uart_bitbang_is_enabled() && GREAD(PINMUX, DIOB5_SEL); } -static void uartn_tx_connect(int uart) +/** + * Connect the UART pin to the given signal + * + * @param uart the uart peripheral number + * @param signal the pinmux selector value for the gpio or peripheral + * function. 0 to disable the output. + */ +static void uart_select_tx(int uart, int signal) { - /* Connect the TX pin to UART peripheral */ if (uart == UART_AP) { - GWRITE(PINMUX, DIOA7_SEL, GC_PINMUX_UART1_TX_SEL); + GWRITE(PINMUX, DIOA7_SEL, signal); } else { - GWRITE(PINMUX, DIOB5_SEL, GC_PINMUX_UART2_TX_SEL); + GWRITE(PINMUX, DIOB5_SEL, signal); /* Remove the pulldown when we are driving the signal */ - GWRITE_FIELD(PINMUX, DIOB5_CTL, PD, 0); + GWRITE_FIELD(PINMUX, DIOB5_CTL, PD, signal ? 0 : 1); } } -static void uartn_tx_disconnect(int uart) +void uartn_tx_connect(int uart) { - /* Disconnect the TX pin from UART peripheral */ + /* + * Don't drive TX unless the debug cable is connected (we have + * something to transmit) and servo is disconnected (we won't be + * drive-fighting with servo). + */ + if (servo_is_connected() || !ccd_ext_is_enabled()) + return; + if (uart == UART_AP) { - GWRITE(PINMUX, DIOA7_SEL, 0); + if (!ccd_is_cap_enabled(CCD_CAP_GSC_TX_AP_RX)) + return; + + if (!ap_uart_is_on()) + return; + + uart_select_tx(UART_AP, GC_PINMUX_UART1_TX_SEL); } else { - GWRITE(PINMUX, DIOB5_SEL, 0); + if (!ccd_is_cap_enabled(CCD_CAP_GSC_TX_EC_RX)) + return; + + if (!ec_is_on()) + return; - /* Set up the pulldown */ - GWRITE_FIELD(PINMUX, DIOB5_CTL, PD, 1); + uart_select_tx(UART_EC, GC_PINMUX_UART2_TX_SEL); } } +void uartn_tx_disconnect(int uart) +{ + /* Disconnect the TX pin from UART peripheral */ + uart_select_tx(uart, 0); +} + /* * Flags for the current CCD device state. This is used for determining what * hardware devices we've enabled now, and which we want enabled. @@ -142,12 +162,6 @@ enum ccd_state_flag { /* SPI port is enabled for AP and/or EC flash */ CCD_ENABLE_SPI = BIT(6), - - /* EC data bridging from UART to USB is enabled. */ - CCD_ENABLE_USB_FROM_UART_EC = BIT(7), - - /* EC data bridging from USB to UART is enabled. */ - CCD_ENABLE_USB_TO_UART_EC = BIT(8), }; int console_is_restricted(void) @@ -182,11 +196,6 @@ static uint32_t get_state_flags(void) if (ccd_usb_spi.state->enabled_device) flags_now |= CCD_ENABLE_SPI; - if (uart_ec_bridge_is_enabled()) - flags_now |= CCD_ENABLE_USB_FROM_UART_EC; - if (uart_ec_bridge_tx_is_enabled()) - flags_now |= CCD_ENABLE_USB_TO_UART_EC; - return flags_now; } @@ -212,10 +221,6 @@ static void print_state_flags(enum console_channel channel, uint32_t flags) cprintf(channel, " I2C"); if (flags & CCD_ENABLE_SPI) cprintf(channel, " SPI"); - if (flags & CCD_ENABLE_USB_FROM_UART_EC) - cprintf(channel, " USBEC"); - if (flags & CCD_ENABLE_USB_TO_UART_EC) - cprintf(channel, "+TX"); } static void ccd_state_change_hook(void) @@ -229,18 +234,11 @@ static void ccd_state_change_hook(void) /* Start out by figuring what flags we might want enabled */ - /* Enable AP UART RX if that device is on */ + /* Enable EC/AP UART RX if that device is on */ if (ap_uart_is_on()) flags_want |= CCD_ENABLE_UART_AP; - /* - * Enable EC UART RX. - * Checking that EC is off (ec_is_rx_allowed()) will be done in the end, - * and CCD_ENABLE_UART_EC will be cleared if so. This is to guarantee - * that EC UART RX won't be enabled if EC is off even with any codes - * overriding this flag. We also intend to keep ec_is_rx_allowed() - * called once. - */ - flags_want |= CCD_ENABLE_UART_EC; + if (ec_is_rx_allowed()) + flags_want |= CCD_ENABLE_UART_EC; #ifdef CONFIG_UART_BITBANG if (uart_bitbang_is_wanted()) @@ -253,8 +251,6 @@ static void ccd_state_change_hook(void) */ if (ccd_ext_is_enabled()) flags_want |= (CCD_ENABLE_UART_AP_TX | CCD_ENABLE_UART_EC_TX | - CCD_ENABLE_USB_FROM_UART_EC | - CCD_ENABLE_USB_TO_UART_EC | CCD_ENABLE_I2C | CCD_ENABLE_SPI); else flags_want = 0; @@ -273,14 +269,9 @@ static void ccd_state_change_hook(void) if (!ccd_is_cap_enabled(CCD_CAP_GSC_TX_AP_RX)) flags_want &= ~CCD_ENABLE_UART_AP_TX; if (!ccd_is_cap_enabled(CCD_CAP_GSC_RX_EC_TX)) - flags_want &= ~CCD_ENABLE_USB_FROM_UART_EC; - /* - * UART_EC TX needs to be disconnected as well as USB RX, otherwise - * Servo is not detectable. - */ + flags_want &= ~CCD_ENABLE_UART_EC; if (!ccd_is_cap_enabled(CCD_CAP_GSC_TX_EC_RX)) flags_want &= ~(CCD_ENABLE_UART_EC_TX | - CCD_ENABLE_USB_TO_UART_EC | CCD_ENABLE_UART_EC_BITBANG); if (!ccd_is_cap_enabled(CCD_CAP_I2C)) flags_want &= ~CCD_ENABLE_I2C; @@ -303,32 +294,12 @@ static void ccd_state_change_hook(void) if (ccd_block & CCD_BLOCK_EC_UART) flags_want &= ~CCD_ENABLE_UART_EC; - /* - * EC UART flags are cleared if ccd ext is not detected or if ccd block - * EC UART is enabled. EC-CR50 comm trumps both of those conditions. - * Re-enable the EC UART flags if EC-CR50 comm is enabled and - * CCD_BLOCK_EC_CR50_COMM must be off in ccd_block bitmap. - */ - if (ec_comm_is_uart_in_packet_mode(UART_EC) && - !(ccd_block & CCD_BLOCK_EC_CR50_COMM)) - flags_want |= (CCD_ENABLE_UART_EC | CCD_ENABLE_UART_EC_TX); - - /* - * Disable EC UART RX if that device is off, otherwise there will be - * an UART interrupt storm. - */ - if (!ec_is_rx_allowed()) - flags_want &= ~CCD_ENABLE_UART_EC; - /* UARTs are either RX-only or RX+TX, so no RX implies no TX */ if (!(flags_want & CCD_ENABLE_UART_AP)) flags_want &= ~CCD_ENABLE_UART_AP_TX; if (!(flags_want & CCD_ENABLE_UART_EC)) flags_want &= ~CCD_ENABLE_UART_EC_TX; - uart_ec_bridge_enable(flags_want & CCD_ENABLE_USB_FROM_UART_EC, - flags_want & CCD_ENABLE_USB_TO_UART_EC); - /* If no change, we're done */ if (flags_now == flags_want) return; @@ -450,8 +421,6 @@ static void print_ccd_ports_blocked(void) ccputs("\nWARNING: enabling UART while servo is connected may " "damage hardware"); } - if (ccd_block & CCD_BLOCK_EC_CR50_COMM) - ccputs(" EC_CR50_COMM"); if (!ccd_block) ccputs(" (none)"); ccputs("\n"); @@ -494,8 +463,6 @@ static int command_ccd_block(int argc, char **argv) block_flag = CCD_BLOCK_SERVO_SHARED; else if (!strcasecmp(argv[1], "IGNORE_SERVO")) block_flag = CCD_BLOCK_IGNORE_SERVO; - else if (!strcasecmp(argv[1], "EC_CR50_COMM")) - block_flag = CCD_BLOCK_EC_CR50_COMM; else return EC_ERROR_PARAM1; @@ -509,8 +476,6 @@ static int command_ccd_block(int argc, char **argv) if (block_flag == CCD_BLOCK_IGNORE_SERVO) servo_ignore(new_state); - else if (block_flag == CCD_BLOCK_EC_CR50_COMM) - ec_comm_block(new_state); /* Update blocked state in deferred function */ ccd_update_state(); @@ -521,6 +486,5 @@ static int command_ccd_block(int argc, char **argv) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(ccdblock, command_ccd_block, - "[<AP | EC | SERVO | IGNORE_SERVO | EC_CR50_COMM>" - " [BOOLEAN]]", + "[<AP | EC | SERVO | IGNORE_SERVO> [BOOLEAN]]", "Force CCD ports disabled"); diff --git a/board/cr50/servo_state.c b/board/cr50/servo_state.c index 4e3cdff27c..f6ded01dd0 100644 --- a/board/cr50/servo_state.c +++ b/board/cr50/servo_state.c @@ -6,7 +6,6 @@ */ #include "common.h" #include "console.h" -#include "ec_comm.h" #include "gpio.h" #include "hooks.h" #include "uart_bitbang.h" @@ -147,18 +146,6 @@ static void servo_detect(void) if (state == DEVICE_STATE_IGNORED) return; - /* - * During EC-CR50 communication, do not change servo state because - * GPIO_DETECT_SERVO (DIOB5) is not available. Return now, and - * let it try to detect in the next second. - * - * Note: Though servo is not detectable, we do not want to change - * servo_state as UNDETECTABLE, otherwise "servo_is_connected()" - * might return false while servo is connected. - */ - if (ec_comm_is_uart_in_packet_mode(UART_EC)) - return; - /* If we're driving EC UART TX, we can't detect servo */ if (!servo_detectable()) { /* We're driving one port; might as well drive them all */ diff --git a/board/cr50/tpm2/NVMem.c b/board/cr50/tpm2/NVMem.c index 052165d5b6..e1a14b4536 100644 --- a/board/cr50/tpm2/NVMem.c +++ b/board/cr50/tpm2/NVMem.c @@ -14,12 +14,9 @@ #include "Platform.h" #include "PlatformData.h" -#include "TPM_Types.h" #include "TpmError.h" #include "assert.h" -#include "ec_comm.h" #include "nvmem.h" -#include "tpm_nvmem.h" /* Local state */ static struct { @@ -191,9 +188,3 @@ void _plat__ClearNvAvail(void) local_state.s_NvIsAvailable = FALSE; return; } - -void _plat__NvInformIndexDataChanged(unsigned int handle) -{ - if (handle == (HR_NV_INDEX + KERNEL_NV_INDEX)) - ec_efs_refresh(); -} diff --git a/board/cr50/tpm_nvmem_ops.c b/board/cr50/tpm_nvmem_ops.c index 23a8ead1cf..9c29834756 100644 --- a/board/cr50/tpm_nvmem_ops.c +++ b/board/cr50/tpm_nvmem_ops.c @@ -28,7 +28,7 @@ enum tpm_read_rv read_tpm_nvmem(uint16_t obj_index, handle_addr = NvEarlyStageFindHandle(object_handle); if (!handle_addr) { CPRINTF("%s: object at 0x%x not found\n", __func__, obj_index); - return TPM_READ_NOT_FOUND; + return tpm_read_not_found; } /* Get properties of this index as stored in nvmem. */ @@ -47,14 +47,14 @@ enum tpm_read_rv read_tpm_nvmem(uint16_t obj_index, if (obj_size > nvIndex.publicArea.dataSize) { CPRINTF("%s: object at 0x%x is smaller than %d\n", __func__, obj_index, obj_size); - return TPM_READ_TOO_SMALL; + return tpm_read_too_small; } /* Perform the read. */ NvReadIndexData(object_handle, &nvIndex, handle_addr, 0, obj_size, obj_value); - return TPM_READ_SUCCESS; + return tpm_read_success; } enum tpm_read_rv read_tpm_nvmem_hidden(uint16_t object_index, @@ -64,9 +64,9 @@ enum tpm_read_rv read_tpm_nvmem_hidden(uint16_t object_index, if (NvGetHiddenObject(HR_HIDDEN | object_index, object_size, obj_value) == TPM_RC_SUCCESS) { - return TPM_READ_SUCCESS; + return tpm_read_success; } else { - return TPM_READ_NOT_FOUND; + return tpm_read_not_found; } } @@ -75,7 +75,7 @@ enum tpm_write_rv write_tpm_nvmem_hidden(uint16_t object_index, void *obj_value, int commit) { - enum tpm_write_rv ret = TPM_WRITE_FAIL; + enum tpm_write_rv ret = tpm_write_fail; uint32_t handle = object_index | HR_HIDDEN; @@ -83,15 +83,15 @@ enum tpm_write_rv write_tpm_nvmem_hidden(uint16_t object_index, NvAddHiddenObject(handle, object_size, obj_value) == TPM_RC_SUCCESS) { - ret = TPM_WRITE_CREATED; + ret = tpm_write_created; } else if (NvWriteHiddenObject(handle, object_size, obj_value) == TPM_RC_SUCCESS) { - ret = TPM_WRITE_UPDATED; + ret = tpm_write_updated; } if (commit && !NvCommit()) - ret = TPM_WRITE_FAIL; + ret = tpm_write_fail; return ret; } diff --git a/board/cr50/tpm_nvmem_ops.h b/board/cr50/tpm_nvmem_ops.h index 2476b62b0f..d12eb1bb5f 100644 --- a/board/cr50/tpm_nvmem_ops.h +++ b/board/cr50/tpm_nvmem_ops.h @@ -8,15 +8,15 @@ #define __EC_BOARD_CR50_TPM_NVMEM_OPS_H enum tpm_read_rv { - TPM_READ_SUCCESS, - TPM_READ_NOT_FOUND, - TPM_READ_TOO_SMALL, + tpm_read_success, + tpm_read_not_found, + tpm_read_too_small }; enum tpm_write_rv { - TPM_WRITE_CREATED, - TPM_WRITE_UPDATED, - TPM_WRITE_FAIL, + tpm_write_created, + tpm_write_updated, + tpm_write_fail }; enum tpm_nv_hidden_object { diff --git a/board/cr50/u2f.c b/board/cr50/u2f.c index b9ad2de20a..b99722e48f 100644 --- a/board/cr50/u2f.c +++ b/board/cr50/u2f.c @@ -87,7 +87,7 @@ static int load_state(struct u2f_state *state) } if (read_tpm_nvmem_hidden(TPM_HIDDEN_U2F_KEK, sizeof(state->salt_kek), - state->salt_kek) == TPM_READ_NOT_FOUND) { + state->salt_kek) == tpm_read_not_found) { /* * Not found means that we have not used u2f before, * or not used it with updated fw that resets kek seed @@ -114,13 +114,13 @@ static int load_state(struct u2f_state *state) if (write_tpm_nvmem_hidden(TPM_HIDDEN_U2F_KEK, sizeof(state->salt_kek), state->salt_kek, - 1 /* commit */) != TPM_WRITE_CREATED) + 1 /* commit */) != tpm_write_created) return 0; } if (read_tpm_nvmem_hidden(TPM_HIDDEN_U2F_KH_SALT, sizeof(state->salt_kh), - state->salt_kh) == TPM_READ_NOT_FOUND) { + state->salt_kh) == tpm_read_not_found) { /* * We have never used u2f before - generate * new seed. @@ -131,7 +131,7 @@ static int load_state(struct u2f_state *state) if (write_tpm_nvmem_hidden(TPM_HIDDEN_U2F_KH_SALT, sizeof(state->salt_kh), state->salt_kh, - 1 /* commit */) != TPM_WRITE_CREATED) + 1 /* commit */) != tpm_write_created) return 0; } @@ -285,7 +285,7 @@ int u2f_gen_kek_seed(int commit) return EC_ERROR_HW_INTERNAL; if (write_tpm_nvmem_hidden(TPM_HIDDEN_U2F_KEK, sizeof(state->salt_kek), - state->salt_kek, commit) == TPM_WRITE_FAIL) + state->salt_kek, commit) == tpm_write_fail) return EC_ERROR_UNKNOWN; return EC_SUCCESS; diff --git a/board/cr50/wp.c b/board/cr50/wp.c index 55c7edcdc4..8e9be0edeb 100644 --- a/board/cr50/wp.c +++ b/board/cr50/wp.c @@ -446,11 +446,11 @@ int board_fwmp_allows_unlock(void) allows_unlock = 0; break; - case TPM_READ_NOT_FOUND: + case tpm_read_not_found: allows_unlock = 1; break; - case TPM_READ_SUCCESS: + case tpm_read_success: allows_unlock = !lock_enforced(&fwmp); break; } @@ -465,7 +465,7 @@ int board_fwmp_fips_mode_enabled(void) { struct RollbackSpaceFirmware fw; - if (TPM_READ_SUCCESS == + if (tpm_read_success == read_tpm_nvmem(FIRMWARE_NV_INDEX, sizeof(fw), &fw)) { return !!(fw.flags & FWMP_DEV_FIPS_MODE); } @@ -478,7 +478,7 @@ int board_vboot_dev_mode_enabled(void) { struct RollbackSpaceFirmware fw; - if (TPM_READ_SUCCESS == + if (tpm_read_success == read_tpm_nvmem(FIRMWARE_NV_INDEX, sizeof(fw), &fw)) { return !!(fw.flags & FIRMWARE_FLAG_DEV_MODE); } diff --git a/board/host/board.c b/board/host/board.c index b4e125efdd..408bfdcf0b 100644 --- a/board/host/board.c +++ b/board/host/board.c @@ -5,7 +5,6 @@ /* Emulator board-specific configuration */ #include "button.h" -#include "ec_comm.h" #include "extpower.h" #include "gpio.h" #include "host_command.h" @@ -68,27 +67,3 @@ const struct i2c_port_t i2c_ports[] = { const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); #endif - -test_mockable void ccd_update_state(void) -{ - -} - -test_mockable void ec_comm_packet_mode_en(enum gpio_signal unsed) -{ - -} - -test_mockable void ec_comm_packet_mode_dis(enum gpio_signal unsed) -{ - -} - -int board_has_ec_cr50_comm_support(void) -{ -#ifdef CONFIG_EC_EFS_SUPPORT - return 1; -#else - return 0; -#endif -} diff --git a/board/host/board.h b/board/host/board.h index 1a5c674adb..ee796df1f0 100644 --- a/board/host/board.h +++ b/board/host/board.h @@ -72,23 +72,7 @@ extern const int supplier_priority[]; #define PD_MIN_CURRENT_MA 500 #define PD_MIN_POWER_MW 7500 -/* UART indexes (use define rather than enum to expand them) */ -enum { - UART_DEFAULT = 0, - UART_CR50 = 0, - UART_AP = 1, - UART_EC = 2, - UART_COUNT, - - UART_NULL = 0xff, -}; - /* Let the tests always check the other NVMEM slot. */ static inline int board_nvmem_legacy_check_needed(void){ return 1; } -/* Mock functions for EC-CR50 communication test */ -int board_has_ec_cr50_comm_support(void); -void board_reboot_ec_deferred(int usec_delay); -void ccd_update_state(void); - #endif /* __CROS_EC_BOARD_H */ diff --git a/board/host/gpio.inc b/board/host/gpio.inc index d0d7e1bbc7..7695a6021d 100644 --- a/board/host/gpio.inc +++ b/board/host/gpio.inc @@ -14,11 +14,6 @@ GPIO_INT(AC_PRESENT, PIN(0, 2), GPIO_INT_BOTH, extpower_interrupt) GPIO_INT(BUTTON_VOLUME_DOWN_L, PIN(0, 3), GPIO_INT_BOTH, button_interrupt) GPIO_INT(BUTTON_VOLUME_UP, PIN(0, 4), GPIO_INT_BOTH, button_interrupt) GPIO_INT(CHARGE_DONE, PIN(0, 5), GPIO_INT_BOTH, inductive_charging_interrupt) -/* GPIOs for EC-CR50 communication */ -GPIO_INT(EC_PACKET_MODE_EN, PIN(0, 16), GPIO_INT_RISING, - ec_comm_packet_mode_en) -GPIO_INT(EC_PACKET_MODE_DIS, PIN(0, 17), GPIO_INT_FALLING, - ec_comm_packet_mode_dis) GPIO(EC_INT_L, PIN(0, 6), 0) GPIO(WP, PIN(0, 7), 0) diff --git a/board/host/tpm_nvmem_ops.h b/board/host/tpm_nvmem_ops.h deleted file mode 100644 index f2090f7733..0000000000 --- a/board/host/tpm_nvmem_ops.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __EC_BOARD_CR50_TPM_NVMEM_OPS_H -#define __EC_BOARD_CR50_TPM_NVMEM_OPS_H - -enum tpm_read_rv { - TPM_READ_SUCCESS, - TPM_READ_NOT_FOUND, - TPM_READ_TOO_SMALL, -}; - -enum tpm_write_rv { - TPM_WRITE_CREATED, - TPM_WRITE_UPDATED, - TPM_WRITE_FAIL, -}; - -enum tpm_nv_hidden_object { - TPM_HIDDEN_U2F_KEK, - TPM_HIDDEN_U2F_KH_SALT, -}; - -enum tpm_read_rv read_tpm_nvmem(uint16_t object_index, - uint16_t object_size, - void *obj_value); - -#endif /* ! __EC_BOARD_CR50_TPM_NVMEM_OPS_H */ diff --git a/chip/g/build.mk b/chip/g/build.mk index 6846d5685c..248f19d1e5 100644 --- a/chip/g/build.mk +++ b/chip/g/build.mk @@ -79,6 +79,7 @@ chip-$(CONFIG_WATCHDOG)+=watchdog.o chip-$(CONFIG_USB)+=usb.o usb_endpoints.o chip-$(CONFIG_USB_CONSOLE)+=usb_console.o +chip-$(CONFIG_USB_HID_KEYBOARD)+=usb_hid_keyboard.o chip-$(CONFIG_USB_BLOB)+=blob.o chip-$(CONFIG_USB_SPI)+=usb_spi.o chip-$(CONFIG_RDD)+=rdd.o diff --git a/chip/g/gpio.c b/chip/g/gpio.c index b5bf0f43d1..46a1e4ed14 100644 --- a/chip/g/gpio.c +++ b/chip/g/gpio.c @@ -51,34 +51,6 @@ void gpio_set_level(enum gpio_signal signal, int value) set_one_gpio_bit(g->port, g->mask, value); } -static void configure_wakepin(int bitmask, uint32_t flags) -{ - /* not VIOn ! */ - if (bitmask > GC_PINMUX_EXITEN0_DIOB7_MASK) - return; - - if (!(flags & DIO_WAKE_EN0)) { - /* Disable the pin */ - GREG32(PINMUX, EXITEN0) &= ~bitmask; - return; - } - - /* level (0) or edge sensitive (1) */ - if (flags & DIO_WAKE_EDGE0) - GREG32(PINMUX, EXITEDGE0) |= bitmask; - else - GREG32(PINMUX, EXITEDGE0) &= ~bitmask; - - /* high/rising (0) or low/falling (1) */ - if (flags & DIO_WAKE_INV0) - GREG32(PINMUX, EXITINV0) |= bitmask; - else - GREG32(PINMUX, EXITINV0) &= ~bitmask; - - /* Enable the pin */ - GREG32(PINMUX, EXITEN0) |= bitmask; -} - int gpio_get_flags_by_mask(uint32_t port, uint32_t mask) { uint32_t flags = 0; @@ -151,50 +123,6 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* No way to trigger on both rising and falling edges, darn it. */ } -void gpio_set_wakepin(enum gpio_signal signal, uint32_t flags) -{ - const struct gpio_info *g = gpio_list + signal; - const int gpio_bitnum = GPIO_MASK_TO_NUM(g->mask); - const int dio_val = GET_GPIO_SEL_REG(g->port, gpio_bitnum); - int dio_mask; - int dio_wake_flags; - - /* Can't do anything if the gpio is not connected to a pin */ - if (!dio_val) - return; - - /* Convert the gpio wake flags to the dio wake pin configuration */ - flags &= GPIO_HIB_WAKE_MASK; - switch (flags) { - case 0: /* Disable Wakepin */ - dio_wake_flags = 0; - break; - case GPIO_HIB_WAKE_HIGH: - dio_wake_flags = DIO_WAKE_HIGH; - break; - case GPIO_HIB_WAKE_LOW: - dio_wake_flags = DIO_WAKE_LOW; - break; - case GPIO_HIB_WAKE_RISING: - dio_wake_flags = DIO_WAKE_RISING; - break; - case GPIO_HIB_WAKE_FALLING: - dio_wake_flags = DIO_WAKE_FALLING; - break; - default: - /* Wake contions cannot be more than one. */ - return; - } - - /* - * GC_PINMUX_{PIN}_SEL values start from 0x1e (DIOM0) - * down to 0x03 (DIOB7). Meanwhile, GC_PINMUX_{wake_cond}_{pin}_MASK - * has BIT(0) for DIOM0 and BIT(27) for DIOB7. - */ - dio_mask = 1 << (GC_PINMUX_DIOM0_SEL - dio_val); - configure_wakepin(dio_mask, dio_wake_flags); -} - void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) { /* This HW feature is not present in the Cr50 ARM core */ @@ -302,6 +230,7 @@ static int connect_dio_to_gpio(struct pinmux const *p) static void connect_pinmux(struct pinmux const *p) { + uint32_t bitmask; int is_input; if (p->flags & DIO_ENABLE_DIRECT_INPUT) { @@ -335,14 +264,24 @@ static void connect_pinmux(struct pinmux const *p) DIO_CTL_PD_LSB, 1); /* Enable any wake pins needed to exit low-power modes */ - if (p->flags & DIO_WAKE_EN0) { - /* - * p->dio.offset is the offset of GC_PINMUX_*_SEL register. - * The next GC_PINMUX_*_SEL register is 8 byte away. - */ - const uint32_t dio_mask = (1 << (p->dio.offset / 8)); - - configure_wakepin(dio_mask, p->flags); + if ((p->flags & DIO_WAKE_EN0) && + (p->dio.offset <= GC_PINMUX_DIOB7_SEL_OFFSET)) { /* not VIOn ! */ + bitmask = BIT((p->dio.offset / 8)); + + /* enable pad as wake source */ + GREG32(PINMUX, EXITEN0) |= bitmask; + + /* level (0) or edge sensitive (1) */ + if (p->flags & DIO_WAKE_EDGE0) + GREG32(PINMUX, EXITEDGE0) |= bitmask; + else + GREG32(PINMUX, EXITEDGE0) &= ~bitmask; + + /* high/rising (0) or low/falling (1) */ + if (p->flags & DIO_WAKE_INV0) + GREG32(PINMUX, EXITINV0) |= bitmask; + else + GREG32(PINMUX, EXITINV0) &= ~bitmask; } } diff --git a/chip/g/init_chip.h b/chip/g/init_chip.h index a5c08cd3d9..506dfeab21 100644 --- a/chip/g/init_chip.h +++ b/chip/g/init_chip.h @@ -23,7 +23,6 @@ * SCRATCH17 - deep sleep count * SCRATCH18 - Preserving USB_DCFG through deep sleep * SCRATCH19 - Preserving USB data sequencing PID through deep sleep - * SCRATCH20 - Preserving EC-EFS context * * PWRDN_SCRATCH 28 - 31 - Reserved for boot rom */ diff --git a/chip/g/sps.c b/chip/g/sps.c index b64e1d1a7b..7f8b81de9b 100644 --- a/chip/g/sps.c +++ b/chip/g/sps.c @@ -255,8 +255,10 @@ static void sps_init(void) GWRITE_FIELD(PINMUX, DIOA10_CTL, IE, 0); /* SPS_MISO */ GWRITE_FIELD(PINMUX, DIOA12_CTL, IE, 1); /* SPS_CS_L */ - /* Configure the SPS_CS_L signal, DIOA12, as wake falling */ - gpio_set_wakepin(GPIO_STRAP_B1, GPIO_HIB_WAKE_FALLING); + /* Allow SPS_CS_L to wake from sleep */ + GWRITE_FIELD(PINMUX, EXITEN0, DIOA12, 1); /* enable powerdown exit */ + GWRITE_FIELD(PINMUX, EXITEDGE0, DIOA12, 1); /* edge sensitive */ + GWRITE_FIELD(PINMUX, EXITINV0, DIOA12, 1); /* wake on low */ } DECLARE_HOOK(HOOK_INIT, sps_init, HOOK_PRIO_DEFAULT); diff --git a/chip/g/uartn.h b/chip/g/uartn.h index e0d0c140b3..bfb7772518 100644 --- a/chip/g/uartn.h +++ b/chip/g/uartn.h @@ -82,6 +82,12 @@ void uartn_tx_stop(int uart); */ int uart_tx_is_connected(int uart); +/* Connect TX pin for the UART */ +void uartn_tx_connect(int uart); + +/* Disconnect TX pin for the UART */ +void uartn_tx_disconnect(int uart); + /** * Return non-zero if TX and RX are enabled for the UART. * diff --git a/chip/g/usart.c b/chip/g/usart.c index 7389d9a911..0a08d261b8 100644 --- a/chip/g/usart.c +++ b/chip/g/usart.c @@ -3,9 +3,6 @@ * found in the LICENSE file. */ -#ifdef BOARD_CR50 -#include "ec_comm.h" -#endif #include "queue.h" #include "queue_policies.h" #ifdef CONFIG_STREAM_SIGNATURE @@ -132,33 +129,6 @@ USB_STREAM_CONFIG(ec_usb, ec_uart_to_usb) #endif -#ifdef BOARD_CR50 -static uint8_t ec_bridge_enabled_; -static uint8_t ec_bridge_tx_enabled_; - -void uart_ec_bridge_enable(int enable, int write) -{ - write = enable && write; - - if (write && !ec_bridge_tx_enabled_) - task_trigger_irq(GC_IRQNUM_UART2_TXINT); - - ec_bridge_enabled_ = enable; - ec_bridge_tx_enabled_ = write; -} - -int uart_ec_bridge_is_enabled(void) -{ - return !!ec_bridge_enabled_; -} - -int uart_ec_bridge_tx_is_enabled(void) -{ - return !!ec_bridge_tx_enabled_; -} - -#endif /* BOARD_CR50 */ - void get_data_from_usb(struct usart_config const *config) { struct queue const *uart_out = config->consumer.queue; @@ -184,43 +154,13 @@ void send_data_to_usb(struct usart_config const *config) q_room = queue_space(uart_in); + if (!q_room) + return; + mask = uart_in->buffer_units_mask; tail = uart_in->state->tail & mask; count = 0; -#ifdef BOARD_CR50 - if (ec_comm_is_uart_in_packet_mode(uart)) { - /* - * Even if UART-to-USB data queue is full (count == q_room), - * It should drain UART queue, so that an EC packet - * can be processed. In this case, EC console data - * shall be lost anyway. - */ - while (uartn_rx_available(uart)) { - uint8_t ch = uartn_read_char(uart); - - if (ec_comm_process_packet(ch)) - continue; - - if ((count != q_room) && uart_ec_bridge_is_enabled()) { - uart_in->buffer[tail] = ch; - tail = (tail + 1) & mask; - count++; - } - } - if (count) - queue_advance_tail(uart_in, count); - return; - } - - /* - * If UART-to-USB bridging is not allowed, do not put any output - * data to uart_in queue. - */ - if ((uart == UART_EC) && !uart_ec_bridge_is_enabled()) - return; -#endif /* BOARD_CR50 */ - while ((count != q_room) && uartn_rx_available(uart)) { uart_in->buffer[tail] = uartn_read_char(uart); tail = (tail + 1) & mask; @@ -247,35 +187,6 @@ static void uart_written(struct consumer const *consumer, size_t count) } #endif -#ifdef BOARD_CR50 - if (config->uart == UART_EC) { - /* - * If USB-to-UART bridging is disabled, do not forward data. - * Otherwise, data could be pushed into UART TX FIFO, and - * transferred to EC eventually once EC-CR50 communication - * enables EC UART. - */ - if (!uart_ec_bridge_tx_is_enabled()) { - /* - * Empty the RX queue, so that host won't suffer from - * congestion. Also, if data remains in the queue, then - * they might be transferred when UART TX gets enabled - * in future. - */ - queue_advance_head(consumer->queue, - queue_count(consumer->queue)); - return; - } - - /* - * If EC-CR50 communication is on-going, then let's not forward - * console input to EC for now. - */ - if (ec_comm_is_uart_in_packet_mode(UART_EC)) - return; - } -#endif /* BOARD_CR50 */ - if (uartn_tx_ready(config->uart) && queue_count(consumer->queue)) uartn_tx_start(config->uart); } diff --git a/chip/g/usart.h b/chip/g/usart.h index 2d9f04974f..cd3a9cfe40 100644 --- a/chip/g/usart.h +++ b/chip/g/usart.h @@ -74,13 +74,4 @@ void get_data_from_usb(struct usart_config const *config); /* Helper for UART bitbang mode. */ extern struct usart_config const ec_uart; -/* Change EC UART-USB Bridge status */ -void uart_ec_bridge_enable(int enabled, int write); - -/* Return non-zero if EC UART-USB Bridge is enabled, or 0 otherwise */ -int uart_ec_bridge_is_enabled(void); - -/* Return non-zero if EC UART-USB Bridge is readwritable, or 0 otherwise */ -int uart_ec_bridge_tx_is_enabled(void); - #endif /* __CROS_FORWARD_UART_H */ diff --git a/chip/g/usb_console.c b/chip/g/usb_console.c index d20129a8bb..11bef1de89 100644 --- a/chip/g/usb_console.c +++ b/chip/g/usb_console.c @@ -11,7 +11,6 @@ #include "printf.h" #include "queue.h" #include "registers.h" -#include "stdbool.h" #include "task.h" #include "timer.h" #include "util.h" @@ -22,25 +21,21 @@ #define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) #define USB_CONSOLE_TIMEOUT_US (30 * MSEC) -static bool last_tx_ok = true; +static int last_tx_ok = 1; -static bool is_reset; +static int is_reset; -#if defined(CONFIG_USB_CONSOLE_DEFAULT_DISABLED) -static bool is_enabled; -#else /* * Start enabled, so we can queue early debug output before the board gets * around to calling usb_console_enable(). */ -static bool is_enabled = true; -#endif +static int is_enabled = 1; /* * But start read-only, so we don't accept console input until we explicitly * decide that we're ready for it. */ -static bool is_readonly = true; +static int is_readonly = 1; /* USB-Serial descriptors */ const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = @@ -392,6 +387,6 @@ int usb_vprintf(const char *format, va_list args) void usb_console_enable(int enabled, int readonly) { - is_enabled = !!enabled; - is_readonly = !!readonly; + is_enabled = enabled; + is_readonly = readonly; } diff --git a/chip/g/usb_hid_keyboard.c b/chip/g/usb_hid_keyboard.c new file mode 100644 index 0000000000..62167d93ca --- /dev/null +++ b/chip/g/usb_hid_keyboard.c @@ -0,0 +1,159 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "clock.h" +#include "common.h" +#include "config.h" +#include "console.h" +#include "gpio.h" +#include "hooks.h" +#include "link_defs.h" +#include "registers.h" +#include "task.h" +#include "timer.h" +#include "util.h" +#include "usb_descriptor.h" +#include "usb_hid.h" + +/* Console output macro */ +#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) + +#define HID_REPORT_SIZE 8 + +/* HID descriptors */ +const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_HID) = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = USB_IFACE_HID_KEYBOARD, + .bAlternateSetting = 0, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_HID, + .bInterfaceSubClass = USB_HID_SUBCLASS_BOOT, + .bInterfaceProtocol = USB_HID_PROTOCOL_KEYBOARD, + .iInterface = USB_STR_HID_KEYBOARD_NAME, +}; +const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID, 81) = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x80 | USB_EP_HID_KEYBOARD, + .bmAttributes = 0x03 /* Interrupt endpoint */, + .wMaxPacketSize = HID_REPORT_SIZE, + .bInterval = 32 /* ms polling interval */ +}; +const struct usb_hid_descriptor USB_CUSTOM_DESC(USB_IFACE_HID, hid) = { + .bLength = 9, + .bDescriptorType = USB_HID_DT_HID, + .bcdHID = 0x0100, + .bCountryCode = 0x00, /* Hardware target country */ + .bNumDescriptors = 1, + .desc = { + {.bDescriptorType = USB_HID_DT_REPORT, + .wDescriptorLength = 45} + } +}; + +/* HID : Report Descriptor */ +static const uint8_t report_desc[] = { + 0x05, 0x01, /* Usage Page (Generic Desktop) */ + 0x09, 0x06, /* Usage (Keyboard) */ + 0xA1, 0x01, /* Collection (Application) */ + 0x05, 0x07, /* Usage Page (Key Codes) */ + 0x19, 0xE0, /* Usage Minimum (224) */ + 0x29, 0xE7, /* Usage Maximum (231) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x01, /* Logical Maximum (1) */ + 0x75, 0x01, /* Report Size (1) */ + 0x95, 0x08, /* Report Count (8) */ + 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ + + 0x95, 0x01, /* Report Count (1) */ + 0x75, 0x08, /* Report Size (8) */ + 0x81, 0x01, /* Input (Constant), ;Reserved byte */ + + 0x95, 0x06, /* Report Count (6) */ + 0x75, 0x08, /* Report Size (8) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x65, /* Logical Maximum(101) */ + 0x05, 0x07, /* Usage Page (Key Codes) */ + 0x19, 0x00, /* Usage Minimum (0) */ + 0x29, 0x65, /* Usage Maximum (101) */ + 0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */ + 0xC0, /* End Collection */ + 0x00 /* Padding */ +}; + +static uint8_t hid_ep_buf[HID_REPORT_SIZE]; +static struct g_usb_desc hid_ep_desc; + +void set_keyboard_report(uint64_t rpt) +{ + memcpy(hid_ep_buf, &rpt, sizeof(rpt)); + hid_ep_desc.flags = DIEPDMA_LAST | DIEPDMA_BS_HOST_RDY | DIEPDMA_IOC | + DIEPDMA_TXBYTES(HID_REPORT_SIZE); + /* enable TX */ + GR_USB_DIEPCTL(USB_EP_HID_KEYBOARD) |= DXEPCTL_CNAK | DXEPCTL_EPENA; +} + +static void hid_tx(void) +{ + /* clear IT */ + GR_USB_DIEPINT(USB_EP_HID_KEYBOARD) = 0xffffffff; + return; +} + +static void hid_reset(void) +{ + hid_ep_desc.flags = DIEPDMA_LAST | DIEPDMA_BS_HOST_BSY | DIEPDMA_IOC; + hid_ep_desc.addr = hid_ep_buf; + GR_USB_DIEPDMA(USB_EP_HID_KEYBOARD) = (uint32_t)&hid_ep_desc; + GR_USB_DIEPCTL(USB_EP_HID_KEYBOARD) = DXEPCTL_MPS(HID_REPORT_SIZE) | + DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_INT | + DXEPCTL_TXFNUM(USB_EP_HID_KEYBOARD); + GR_USB_DAINTMSK |= DAINT_INEP(USB_EP_HID_KEYBOARD); +} + +USB_DECLARE_EP(USB_EP_HID_KEYBOARD, hid_tx, hid_tx, hid_reset); + +static int hid_iface_request(struct usb_setup_packet *req) +{ + if ((req->bmRequestType & USB_DIR_IN) && + req->bRequest == USB_REQ_GET_DESCRIPTOR && + req->wValue == (USB_HID_DT_REPORT << 8)) { + /* Setup : HID specific : Get Report descriptor */ + return load_in_fifo(report_desc, + MIN(req->wLength, + sizeof(report_desc))); + } + + /* Anything else we'll stall */ + return -1; +} +USB_DECLARE_IFACE(USB_IFACE_HID_KEYBOARD, hid_iface_request); + +#ifdef CR50_DEV +/* Just for debugging */ +static int command_hid(int argc, char **argv) +{ + uint8_t keycode = 0x0a; /* 'G' key */ + + if (argc >= 2) { + char *e; + + keycode = strtoi(argv[1], &e, 16); + if (*e) + return EC_ERROR_PARAM1; + } + + /* press then release the key */ + set_keyboard_report((uint32_t)keycode << 16); + udelay(50 * MSEC); + set_keyboard_report(0x000000); + + return EC_SUCCESS; +} +DECLARE_CONSOLE_COMMAND(hid, command_hid, + "[<HID keycode>]", + "test USB HID driver"); +#endif diff --git a/chip/host/build.mk b/chip/host/build.mk index 5d85a51128..92284b072a 100644 --- a/chip/host/build.mk +++ b/chip/host/build.mk @@ -8,8 +8,8 @@ CORE:=host -chip-y=clock.o flash.o gpio.o i2c.o lpc.o persistence.o reboot.o registers.o \ - system.o uart.o +chip-y=system.o gpio.o uart.o persistence.o flash.o lpc.o reboot.o i2c.o \ + clock.o chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o chip-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_phy.o diff --git a/chip/host/gpio.c b/chip/host/gpio.c index 00f618c0ec..60ef32d22a 100644 --- a/chip/host/gpio.c +++ b/chip/host/gpio.c @@ -60,12 +60,6 @@ test_mockable int gpio_enable_interrupt(enum gpio_signal signal) return EC_SUCCESS; } -test_mockable int gpio_disable_interrupt(enum gpio_signal signal) -{ - gpio_interrupt_enabled[signal] = 0; - return EC_SUCCESS; -} - test_mockable int gpio_clear_pending_interrupt(enum gpio_signal signal) { return EC_SUCCESS; diff --git a/chip/host/registers.c b/chip/host/registers.c deleted file mode 100644 index fad062ea15..0000000000 --- a/chip/host/registers.c +++ /dev/null @@ -1,36 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Registers for test - */ -#include <stdio.h> -#include <stdlib.h> -#include <string.h> - -#include "common.h" -#include "registers.h" -#include "util.h" - -static struct faux_register_array { - const char * const name; - unsigned int var; -} mock_registers_[] = { - { - .name = GNAME(PMU, PWRDN_SCRATCH20), - }, - - /* Define registers as needed. */ -}; - -void *get_reg_addr(const char * const reg_name) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mock_registers_); i++) - if (!strcmp(mock_registers_[i].name, reg_name)) - return &mock_registers_[i].var; - - fprintf(stderr, "Unknown register is accessed: %s\n", reg_name); - exit(1); -} diff --git a/chip/host/registers.h b/chip/host/registers.h index 7d2d10a9ec..0ee68b8e23 100644 --- a/chip/host/registers.h +++ b/chip/host/registers.h @@ -9,8 +9,3 @@ * There is no register for emulator, but this file exists to prevent * compilation failure if any file includes registers.h */ - -#define GNAME(mname, rname) "GC_ ## mname ## _ ## rname ## _NAME" -#define GREG32(mname, rname) REG32(get_reg_addr(GNAME(mname, rname))) - -void *get_reg_addr(const char * const reg_name); diff --git a/chip/host/uart.c b/chip/host/uart.c index 13caca0c48..9db7f1bfe8 100644 --- a/chip/host/uart.c +++ b/chip/host/uart.c @@ -7,7 +7,6 @@ #include <pthread.h> #include <stdio.h> -#include <stdlib.h> #include <termio.h> #include <unistd.h> @@ -16,7 +15,6 @@ #include "task.h" #include "test_util.h" #include "uart.h" -#include "uartn.h" #include "util.h" static int stopped = 1; @@ -30,69 +28,34 @@ static int char_available; static struct queue const cached_char = QUEUE_NULL(INPUT_BUFFER_SIZE, char); #define CONSOLE_CAPTURE_SIZE 2048 -static struct { - char buf[CONSOLE_CAPTURE_SIZE]; - int size; - int enabled; -} uart_capture[UART_COUNT]; +static char capture_buf[CONSOLE_CAPTURE_SIZE]; +static int capture_size; +static int capture_enabled; - -static void putch_into_captured_buf(int uart, char c, int is_last) -{ - uart_capture[uart].buf[uart_capture[uart].size] = c; - if (!is_last) - uart_capture[uart].size++; -} - -void test_capture_uartn(int uart, int enabled) +void test_capture_console(int enabled) { - if (uart >= UART_COUNT) { - fprintf(stderr, "Unknown UART port accessed: %d\n", uart); - exit(1); - } - - if (enabled == uart_capture[uart].enabled) + if (enabled == capture_enabled) return; if (enabled) - uart_capture[uart].size = 0; + capture_size = 0; else - putch_into_captured_buf(uart, '\0', 1); + capture_buf[capture_size] = '\0'; - uart_capture[uart].enabled = enabled; + capture_enabled = enabled; } -void test_capture_console(int enabled) -{ - test_capture_uartn(UART_DEFAULT, enabled); -} - -static void test_capture_char(int uart, char c) +static void test_capture_char(char c) { - if (uart >= UART_COUNT) { - fprintf(stderr, "Unknown UART port accessed: %d\n", uart); - exit(1); - } - - if (uart_capture[uart].size == CONSOLE_CAPTURE_SIZE) + if (capture_size == CONSOLE_CAPTURE_SIZE) return; - - putch_into_captured_buf(uart, c, 0); + capture_buf[capture_size++] = c; } -const char *test_get_captured_uartn(int uart) -{ - if (uart >= UART_COUNT) { - fprintf(stderr, "Unknown UART port accessed: %d\n", uart); - exit(1); - } - - return uart_capture[uart].buf; -} const char *test_get_captured_console(void) { - return test_get_captured_uartn(UART_DEFAULT); + return (const char *)capture_buf; } static void uart_interrupt(void) @@ -124,7 +87,7 @@ int uart_tx_stopped(void) void uart_tx_flush(void) { - uartn_tx_flush(UART_DEFAULT); + /* Nothing */ } int uart_tx_ready(void) @@ -139,7 +102,10 @@ int uart_rx_available(void) void uart_write_char(char c) { - uartn_write_char(UART_DEFAULT, c); + if (capture_enabled) + test_capture_char(c); + printf("%c", c); + fflush(stdout); } int uart_read_char(void) @@ -204,19 +170,3 @@ void uart_init(void) stopped = 1; /* Not transmitting yet */ init_done = 1; } - -test_mockable void uartn_tx_flush(int uart_unused) -{ - /* Nothing */ -} - -test_mockable void uartn_write_char(int uart, char c) -{ - if (uart_capture[uart].enabled) - test_capture_char(uart, c); - - if (uart == UART_DEFAULT) { - printf("%c", c); - fflush(stdout); - } -} diff --git a/chip/host/uartn.h b/chip/host/uartn.h deleted file mode 100644 index 5056e61bb7..0000000000 --- a/chip/host/uartn.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_UARTN_H -#define __CROS_EC_UARTN_H - -#include "uart.h" - -/** - * Flush the transmit FIFO. - */ -void uartn_tx_flush(int uart); - -/** - * Send a character to the UART data register. - * - * If the transmit FIFO is full, blocks until there is space. - * - * @param c Character to send. - */ -void uartn_write_char(int uart, char c); - - -#endif /* __CROS_EC_UARTN_H */ diff --git a/common/build.mk b/common/build.mk index d1772add2b..038798703a 100644 --- a/common/build.mk +++ b/common/build.mk @@ -51,7 +51,6 @@ common-$(CONFIG_CURVE25519)+=curve25519-generic.o endif common-$(CONFIG_DEVICE_STATE)+=device_state.o common-$(CONFIG_DPTF)+=dptf.o -common-$(CONFIG_EC_EFS_SUPPORT)+=ec_comm.o ec_efs.o common-$(CONFIG_EXTENSION_COMMAND)+=extension.o common-$(CONFIG_EXTPOWER_GPIO)+=extpower_gpio.o common-$(CONFIG_FANS)+=fan.o pwm.o @@ -116,6 +115,7 @@ common-$(CONFIG_USB_PORT_POWER_SMART)+=usb_port_power_smart.o common-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_protocol.o usb_pd_policy.o common-$(CONFIG_USB_PD_LOGGING)+=event_log.o pd_log.o common-$(CONFIG_USB_PD_TCPC)+=usb_pd_tcpc.o +common-$(CONFIG_USB_UPDATE)+=usb_update.o update_fw.o common-$(CONFIG_VBOOT_HASH)+=sha256.o vboot_hash.o common-$(CONFIG_VSTORE)+=vstore.o common-$(CONFIG_WEBUSB_URL)+=webusb_desc.o diff --git a/common/ec_comm.c b/common/ec_comm.c deleted file mode 100644 index 18ea225ef9..0000000000 --- a/common/ec_comm.c +++ /dev/null @@ -1,364 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * EC-CR50 communication - */ -#include "common.h" -#include "console.h" -#include "crc8.h" -#include "ec_comm.h" -#include "gpio.h" -#include "hooks.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "uartn.h" -#include "vboot.h" - -#define CPRINTS(format, args...) cprints(CC_TASK, "EC-COMM: " format, ## args) - -/* - * EC communications state machine (FSM) is supposed to be active between TPM - * reset (including power on) and the moment EC_IN_RW transition is latched. - * - * Each packet is supposed to be prepended by at least one synchronization - * character (0xEC). If packet does not verify, the entire stream contents, - * including all sync characters is delivered to the USB bridge. - * - * Meaning of the states included in the enum below is as follows: - */ -enum ec_comm_phase { - PHASE_READY_COMM = 0, - PHASE_RECEIVING_PREAMBLE, - PHASE_RECEIVING_HEADER, - PHASE_RECEIVING_DATA, -}; - -/* - * Context of EC-CR50 communication - */ -static struct ec_comm_context_ { - uint8_t uart; /* Current UART ID in packet mode. */ - /* UART_NULL if no UART is in packet mode */ - uint8_t phase; /* enum ec_comm_phase */ - uint8_t preamble_count; - uint8_t bytes_received; - - uint8_t bytes_expected; - uint8_t reserved[1]; - - uint16_t last_resp; - - union { - struct cr50_comm_packet ph; - uint8_t packet[CR50_COMM_MAX_PACKET_SIZE]; - }; -} ec_comm_ctx; - - -/* - * Initialize EC-CR50 communication context. - */ -static void ec_comm_init_(void) -{ - ec_comm_ctx.uart = UART_NULL; - - if (!board_has_ec_cr50_comm_support()) - return; - - CPRINTS("Initializtion"); - - gpio_enable_interrupt(GPIO_EC_PACKET_MODE_EN); - gpio_enable_interrupt(GPIO_EC_PACKET_MODE_DIS); - - /* If DIOB3 is already high, then enable the packet mode. */ - if (gpio_get_level(GPIO_EC_PACKET_MODE_EN)) - ec_comm_packet_mode_en(GPIO_EC_PACKET_MODE_EN); -} -DECLARE_HOOK(HOOK_INIT, ec_comm_init_, HOOK_PRIO_INIT_EC_CR50_COMM); - -/* - * Process the received packet. - * - * @param ph Pointer to the received EC-Cr50 packet. - * @param bytes Total bytes of the received EC-Cr50 packet. - * @return CR50_COMM_SUCCESS if the packet has been processed successfully, - * CR50_COMM_ERROR_CRC if CRC is incorrect, - * CR50_COMM_ERROR_UNDEFINED_CMD if the cmd is unknown, - * CR50_COMM_ERROR_SIZE if data size is not as expected, or - * CR50_COMM_ERROR_BAD_PAYLOAD if the given hash and the hash in NVM - * are not same. - * 0 if it deosn't have to respond to EC. - */ -static uint16_t decode_packet_(const struct cr50_comm_packet *ph, int bytes) -{ - const int offset_cmd = offsetof(struct cr50_comm_packet, cmd); - uint8_t crc8_calc; - uint16_t response; - - /* Verify CRC. */ - crc8_calc = crc8((const uint8_t *)&ph->cmd, bytes - offset_cmd); - if (crc8_calc != ph->crc) - return CR50_COMM_ERROR_CRC; - - /* Execute the command. */ - switch (ph->cmd) { - case CR50_COMM_CMD_SET_BOOT_MODE: - response = ec_efs_set_boot_mode(ph->data, ph->size); - break; - - case CR50_COMM_CMD_VERIFY_HASH: - response = ec_efs_verify_hash(ph->data, ph->size); - break; - - default: - response = CR50_COMM_ERROR_UNDEFINED_CMD; - } - - return response; -} - -/* - * Transfer a 'response' to 'uart' port using DIOB3 pin. - * - * @param response Response code to return to EC. Should be one of - * CR50_COMM_RESPONSE codes in include/vboot.h. - */ -static void transfer_response_to_ec_(uint16_t response) -{ - uint8_t *ptr_resp = (uint8_t *)&response; - int uart = ec_comm_ctx.uart; - - /* Send the response to EC in little endian. */ - uartn_write_char(uart, ptr_resp[0]); - uartn_write_char(uart, ptr_resp[1]); - - uartn_tx_flush(uart); /* Flush from UART2_TX to DIOB3 */ - - ec_comm_ctx.last_resp = response; -} - -int ec_comm_process_packet(uint8_t ch) -{ - uint16_t response = 0; - - switch (ec_comm_ctx.phase) { - case PHASE_READY_COMM: - /* - * if it is not the preamble, then return 0 so that ch can be - * forwarded to USB. - */ - if (ch != CR50_COMM_PREAMBLE) { - ec_comm_ctx.preamble_count = 0; - return 0; - } - - /* - * Forward ch to USB even if it is CR50_COMM_PREAMBLE, because - * it is not yet sure whether it is a preamble or not. - * Forwarding 0xec to USB is not harmful anyway. - */ - if (++ec_comm_ctx.preamble_count < MIN_LENGTH_PREAMBLE) - return 0; - - ec_comm_ctx.phase = PHASE_RECEIVING_PREAMBLE; - break; - - case PHASE_RECEIVING_PREAMBLE: - if (ch == CR50_COMM_PREAMBLE) { - ++ec_comm_ctx.preamble_count; - break; - } - - /* - * First non-preamble character. Reset received bytes and - * fall through to receive header. - */ - ec_comm_ctx.bytes_received = 0; - ec_comm_ctx.bytes_expected = sizeof(struct cr50_comm_packet); - ec_comm_ctx.phase = PHASE_RECEIVING_HEADER; - /* FALLTHROUGH */ - - case PHASE_RECEIVING_HEADER: - /* - * Note: EC-CR50 communication is designed to perform in - * little endian. - */ - ec_comm_ctx.packet[ec_comm_ctx.bytes_received++] = ch; - - if (ec_comm_ctx.bytes_received < ec_comm_ctx.bytes_expected) - break; - - /* The header has been received. Let's parse it. */ - if (ec_comm_ctx.ph.magic != CR50_COMM_MAGIC_WORD) { - response = CR50_COMM_ERROR_MAGIC; - break; - } - - /* Check struct_version */ - /* - * Note: if CR50_COMM_VERSION gets bigger than 0x00, - * you should implement how to handle backward - * compatibility. - */ - if (ec_comm_ctx.ph.version != CR50_COMM_VERSION) { - response = CR50_COMM_ERROR_STRUCT_VERSION; - break; - } - - if (ec_comm_ctx.ph.size == 0) { - /* Data size zero, then process the packet now. */ - response = decode_packet_(&ec_comm_ctx.ph, - ec_comm_ctx.bytes_received); - } else if ((ec_comm_ctx.ph.size + ec_comm_ctx.bytes_expected) > - CR50_COMM_MAX_PACKET_SIZE) { - response = CR50_COMM_ERROR_SIZE; - } else { - ec_comm_ctx.bytes_expected += ec_comm_ctx.ph.size; - ec_comm_ctx.phase = PHASE_RECEIVING_DATA; - } - break; - - case PHASE_RECEIVING_DATA: - ec_comm_ctx.packet[ec_comm_ctx.bytes_received++] = ch; - - /* The EC is done sending the packet, let's process it. */ - if (ec_comm_ctx.bytes_received >= ec_comm_ctx.bytes_expected) - response = decode_packet_(&ec_comm_ctx.ph, - ec_comm_ctx.bytes_received); - break; - - default: - /* - * It is in the unknown phase. - * Let's turn the phase back to READY_COMM, and - * return 0 so that ch can be forwarded to USB. - */ - ec_comm_ctx.phase = PHASE_READY_COMM; - ec_comm_ctx.preamble_count = 0; - return 0; - } - - if (response) { - transfer_response_to_ec_(response); - -#ifdef CR50_RELAXED - CPRINTS("decoded a packet"); - CPRINTS("header : 0x%ph", - HEX_BUF((uint8_t *)&ec_comm_ctx.ph, - sizeof(struct cr50_comm_packet))); - CPRINTS("body : 0x%ph", - HEX_BUF((uint8_t *)ec_comm_ctx.ph.data, - ec_comm_ctx.ph.size)); - /* Let's response to EC */ - CPRINTS("response: 0x%04x", response); -#endif - /* - * If it reaches here, EC comm is either broken or one packet - * was well-processed. Let's turn the phase back to READY_COMM. - */ - ec_comm_ctx.phase = PHASE_READY_COMM; - ec_comm_ctx.preamble_count = 0; - } - - return 1; -} - -void ec_comm_packet_mode_en(enum gpio_signal unsed) -{ - disable_sleep(SLEEP_MASK_EC_CR50_COMM); - - /* Initialize packet context */ - ec_comm_ctx.phase = PHASE_READY_COMM; - ec_comm_ctx.preamble_count = 0; - ec_comm_ctx.uart = UART_EC; /* Enable Packet Mode */ - ccd_update_state(); -} - -void ec_comm_packet_mode_dis(enum gpio_signal unsed) -{ - ec_comm_ctx.uart = UART_NULL; /* Disable Packet Mode. */ - ccd_update_state(); - - enable_sleep(SLEEP_MASK_EC_CR50_COMM); -} - -int ec_comm_is_uart_in_packet_mode(int uart) -{ - return uart == ec_comm_ctx.uart; -} - -void ec_comm_block(int block) -{ - static int is_blocked; - - if (is_blocked == block) - return; - - if (block) { - gpio_disable_interrupt(GPIO_EC_PACKET_MODE_EN); - gpio_disable_interrupt(GPIO_EC_PACKET_MODE_DIS); - - if (ec_comm_is_uart_in_packet_mode(UART_EC)) - ec_comm_packet_mode_dis(GPIO_EC_PACKET_MODE_DIS); - } else { - gpio_enable_interrupt(GPIO_EC_PACKET_MODE_EN); - gpio_enable_interrupt(GPIO_EC_PACKET_MODE_DIS); - } - - is_blocked = block; - - /* Note: ccd_update_state() should be called to change UART status. */ -} - -/* - * A console command, printing EC-CR50-Comm status. - */ -static int command_ec_comm(int argc, char **argv) -{ - if (!board_has_ec_cr50_comm_support()) { - ccprintf("No EC-CR50 comm support\n"); - return EC_ERROR_INVAL; - } - - if (argc > 1) { - if (!strcasecmp(argv[1], "corrupt")) { - int result = ec_efs_corrupt_hash(); - - if (result != EC_SUCCESS) - return result; - } else { - return EC_ERROR_PARAM1; - } - /* - * let's keep processing so that we can see how the context - * values are changed. - */ - } - - /* - * EC Packet Context - */ - ccprintf("uart : 0x%02x\n", ec_comm_ctx.uart); - ccprintf("packet mode : %sABLED\n", - ec_comm_is_uart_in_packet_mode(UART_EC) ? "EN" : "DIS"); - - ccprintf("phase : %d\n", ec_comm_ctx.phase); - ccprintf("preamble_count : %d\n", ec_comm_ctx.preamble_count); - ccprintf("bytes_received : %d\n", ec_comm_ctx.bytes_received); - ccprintf("bytes_expected : %d\n", ec_comm_ctx.bytes_expected); -#ifdef CR50_RELAXED - ccprintf("packet:\n"); - hexdump((uint8_t *)ec_comm_ctx.packet, CR50_COMM_MAX_PACKET_SIZE); -#endif /* CR50_RELAXED */ - ccprintf("response : 0x%04x\n", ec_comm_ctx.last_resp); - ccprintf("\n"); - ec_efs_print_status(); - - return EC_SUCCESS; -} -DECLARE_SAFE_CONSOLE_COMMAND(ec_comm, command_ec_comm, - "[corrupt]", - "Dump EC-CR50-comm status" -); diff --git a/common/ec_efs.c b/common/ec_efs.c deleted file mode 100644 index a0b912b9a4..0000000000 --- a/common/ec_efs.c +++ /dev/null @@ -1,347 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * EC-EFS (Early Firmware Selection) - */ -#include "common.h" -#include "console.h" -#include "ec_comm.h" -#include "ccd_config.h" -#include "crc8.h" -#include "ec_commands.h" -#include "extension.h" -#include "hooks.h" -#ifndef BOARD_HOST -#include "Global.h" -#include "NV_fp.h" -#include "nvmem.h" -#endif -#include "registers.h" -#include "system.h" -#include "tpm_nvmem.h" -#include "tpm_nvmem_ops.h" -#include "vboot.h" - -#ifdef CR50_DEV -#define CPRINTS(format, args...) cprints(CC_TASK, "EC-EFS: " format, ## args) -#else -#define CPRINTS(format, args...) do { } while (0) -#endif - -/* - * Context of EC-EFS - */ -static struct ec_efs_context_ { - uint32_t boot_mode:8; /* enum ec_efs_boot_mode */ - uint32_t hash_is_loaded:1; /* Is EC hash loaded from nvmem */ - uint32_t reserved:23; - - uint32_t secdata_error_code; - - uint8_t hash[SHA256_DIGEST_SIZE]; /* EC-RW digest */ -} ec_efs_ctx; - -static const char * const boot_mode_name_[] = { - "NORMAL", - "NO_BOOT", -}; - -/* - * Change the boot mode - * - * @param mode_val New boot mode value to change - */ -static void set_boot_mode_(uint8_t mode_val) -{ - if (ec_efs_ctx.boot_mode != mode_val) - cprints(CC_SYSTEM, "boot_mode: 0x%02x -> 0x%02x", - ec_efs_ctx.boot_mode, mode_val); - - ec_efs_ctx.boot_mode = mode_val; - - /* Backup some ec_efs context to scratch register */ - GREG32(PMU, PWRDN_SCRATCH20) &= ~0xff; - GREG32(PMU, PWRDN_SCRATCH20) |= mode_val; -} - -static int load_ec_hash_(uint8_t * const ec_hash) -{ - struct vb2_secdata_kernel secdata; - const uint8_t secdata_size = sizeof(struct vb2_secdata_kernel); - uint8_t size_to_crc; - uint8_t struct_size; - uint8_t crc; - - if (read_tpm_nvmem(KERNEL_NV_INDEX, secdata_size, - (void *)&secdata) != TPM_READ_SUCCESS) - return EC_ERROR_VBOOT_DATA_UNDERSIZED; - - /* - * Check struct version. CRC offset may be different with old struct - * version - */ - if (secdata.struct_version < VB2_SECDATA_KERNEL_STRUCT_VERSION_MIN) - return EC_ERROR_VBOOT_DATA_INCOMPATIBLE; - - /* Check struct size. */ - struct_size = secdata.struct_size; - if (struct_size != secdata_size) - return EC_ERROR_VBOOT_DATA; - - /* Check CRC */ - size_to_crc = struct_size - - offsetof(struct vb2_secdata_kernel, crc8) - - sizeof(secdata.crc8); - crc = crc8((uint8_t *)&secdata.reserved0, size_to_crc); - if (crc != secdata.crc8) - return EC_ERROR_CRC; - - /* Read hash and copy to hash */ - memcpy(ec_hash, secdata.ec_hash, sizeof(secdata.ec_hash)); - - return EC_SUCCESS; -} - -/* - * Initialize EC-EFS context. - */ -static void ec_efs_init_(void) -{ - if (!board_has_ec_cr50_comm_support()) - return; - - /* - * If it is a wakeup from deep sleep, then recover some core EC-EFS - * context values, including the boot_mode value, from a PWRD_SCRATCH - * register. Otherwise, reset boot_mode. - */ - if (system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE) - set_boot_mode_(GREG32(PMU, PWRDN_SCRATCH20) & 0xff); - else - ec_efs_reset(); - - /* Read an EC hash in kernel secdata (TPM kernel NV index). */ - if (ec_efs_ctx.hash_is_loaded) - return; - - ec_efs_refresh(); -} -DECLARE_HOOK(HOOK_INIT, ec_efs_init_, HOOK_PRIO_INIT_EC_EFS); - -/** - * TPM vendor command handler to respond with EC Boot Mode. - * - * @return VENDOR_RC_SUCCESS - * - */ -static enum vendor_cmd_rc vc_get_boot_mode_(struct vendor_cmd_params *p) -{ - uint8_t *buffer; - - if (!board_has_ec_cr50_comm_support()) - return VENDOR_RC_NO_SUCH_SUBCOMMAND; - - buffer = (uint8_t *)p->buffer; - buffer[0] = (uint8_t)ec_efs_ctx.boot_mode; - - p->out_size = 1; - - return VENDOR_RC_SUCCESS; -} -DECLARE_VENDOR_COMMAND_P(VENDOR_CC_GET_BOOT_MODE, vc_get_boot_mode_); - -/** - * TPM vendor command handler to reset EC. - * - * @return VEDOR_RC_SUCCESS - */ -static enum vendor_cmd_rc vc_reset_ec_(struct vendor_cmd_params *p) -{ - if (!board_has_ec_cr50_comm_support()) - return VENDOR_RC_NO_SUCH_SUBCOMMAND; - - /* - * Let's reset EC a little later so that CR50 can send a TPM command - * to AP. - */ - board_reboot_ec_deferred(50 * MSEC); - - return VENDOR_RC_SUCCESS; -} -DECLARE_VENDOR_COMMAND_P(VENDOR_CC_RESET_EC, vc_reset_ec_); - -void ec_efs_reset(void) -{ - set_boot_mode_(EC_EFS_BOOT_MODE_NORMAL); -} - -/* - * Change the EC boot mode value. - * - * @param data Pointer to the EC-CR50 packet - * @param size Data (payload) size in EC-CR50 packet - * @return CR50_COMM_SUCCESS if the packet has been processed successfully, - * CR50_COMM_ERROR_SIZE if data size is not as expected, or - * 0 if it does not respond to EC. - */ -uint16_t ec_efs_set_boot_mode(const char * const data, const uint8_t size) -{ - uint8_t boot_mode; - - if (size != 1) - return CR50_COMM_ERROR_SIZE; - - boot_mode = data[0]; - - switch (boot_mode) { - case EC_EFS_BOOT_MODE_NORMAL: - /* - * Per EC-EFS2 design, CR50 accepts the repeating commands - * as long as the result is the same. It is to be tolerant - * against CR50 response loss, so that EC can resend the - * same command. - */ - if (ec_efs_ctx.boot_mode == EC_EFS_BOOT_MODE_NORMAL) - break; - /* - * Once the boot mode is NO_BOOT, then it must not be - * set to NORMAL mode without resetting EC. - */ - board_reboot_ec_deferred(0); - return 0; - - case EC_EFS_BOOT_MODE_NO_BOOT: - break; - - default: - return CR50_COMM_ERROR_BAD_PAYLOAD; - } - - set_boot_mode_(boot_mode); - return CR50_COMM_SUCCESS; -} - -/* - * Verify the given EC-FW hash against one in kernel secdata. - * - * @param data Pointer to the EC-CR50 packet - * @param size Data (payload) size in EC-CR50 packet - * @return CR50_COMM_SUCCESS if the packet has been processed successfully, - * CR50_COMM_ERROR_SIZE if data size is not as expected, or - * CR50_COMM_ERROR_BAD_PAYLOAD if the given hash and the hash in NVM - * are not same. - * 0 if it deosn't have to respond to EC. - */ -uint16_t ec_efs_verify_hash(const char *hash_data, const uint8_t size) -{ - if (size != SHA256_DIGEST_SIZE) - return CR50_COMM_ERROR_SIZE; - - if (!ec_efs_ctx.hash_is_loaded) { - if (ec_efs_ctx.secdata_error_code == EC_SUCCESS) - ec_efs_refresh(); - - if (ec_efs_ctx.secdata_error_code != EC_SUCCESS) - return CR50_COMM_ERROR_NVMEM; - } - - if (safe_memcmp(hash_data, ec_efs_ctx.hash, SHA256_DIGEST_SIZE)) { - /* Verification failed */ - set_boot_mode_(EC_EFS_BOOT_MODE_NO_BOOT); - return CR50_COMM_ERROR_BAD_PAYLOAD; - } - - /* - * Once the boot mode is not NORMAL, (i.e. it is NO_BOOT), then CR50 - * should not approve the hash verification, but reset EC. - */ - if (ec_efs_ctx.boot_mode != EC_EFS_BOOT_MODE_NORMAL) { - board_reboot_ec_deferred(0); - return 0; - } - - return CR50_COMM_SUCCESS; -} - -void ec_efs_refresh(void) -{ - int rv; - - if (!board_has_ec_cr50_comm_support()) - return; - - rv = load_ec_hash_(ec_efs_ctx.hash); - if (rv == EC_SUCCESS) { - ec_efs_ctx.hash_is_loaded = 1; - } else { - ec_efs_ctx.hash_is_loaded = 0; - cprints(CC_SYSTEM, "load_ec_hash error: 0x%x", rv); - } - ec_efs_ctx.secdata_error_code = rv; -} - -void ec_efs_print_status(void) -{ - /* EC-EFS Context */ - ccprintf("ec_hash : %sLOADED\n", - ec_efs_ctx.hash_is_loaded ? "" : "UN"); - ccprintf("secdata_error_code : 0x%08x\n", - ec_efs_ctx.secdata_error_code); - ccprintf("boot_mode : %s\n", - boot_mode_name_[ec_efs_ctx.boot_mode]); - -#ifdef CR50_RELAXED - ccprintf("ec_hash_secdata : %ph\n", - HEX_BUF(ec_efs_ctx.hash, SHA256_DIGEST_SIZE)); -#endif -} - -enum ec_error_list ec_efs_corrupt_hash(void) -{ -#ifndef BOARD_HOST - struct vb2_secdata_kernel secdata; - const uint8_t secdata_size = sizeof(struct vb2_secdata_kernel); - TPM_HANDLE object_handle; - NV_INDEX nvIndex; - uint8_t size_to_crc; - int i; - - /* Check CCD is opened */ - if (ccd_get_state() != CCD_STATE_OPENED) { - ccprintf("CCD is not opened\n"); - return EC_ERROR_ACCESS_DENIED; - } - - /* Read the kernel secdata */ - if (read_tpm_nvmem(KERNEL_NV_INDEX, secdata_size, - (void *)&secdata) != TPM_READ_SUCCESS) - return EC_ERROR_VBOOT_DATA_UNDERSIZED; - - /* Modify hash */ - for (i = 0; i < SHA256_DIGEST_SIZE; i++) - secdata.ec_hash[i] = ~ec_efs_ctx.hash[i] + 0x01; - - size_to_crc = secdata_size - - offsetof(struct vb2_secdata_kernel, crc8) - - sizeof(secdata.crc8); - secdata.crc8 = crc8((uint8_t *)&secdata.reserved0, size_to_crc); - - /* Corrupt KERNEL_NV_INDEX in nvmem cache. */ - object_handle = HR_NV_INDEX + KERNEL_NV_INDEX; - NvGetIndexInfo(object_handle, &nvIndex); - NvWriteIndexData(object_handle, &nvIndex, 0, secdata_size, &secdata); - nvmem_unlock_cache(1); - - /* Reload the corrupted ECRW-hash from kernel secdata. */ - ec_efs_refresh(); -#endif - return EC_SUCCESS; -} - -#ifdef BOARD_HOST -uint8_t ec_efs_get_boot_mode(void) -{ - return ec_efs_ctx.boot_mode; -} -#endif diff --git a/common/extension.c b/common/extension.c index 141b15fab9..a1f1d6920e 100644 --- a/common/extension.c +++ b/common/extension.c @@ -31,12 +31,10 @@ uint32_t extension_route_command(struct vendor_cmd_params *p) case VENDOR_CC_INVALIDATE_INACTIVE_RW: case VENDOR_CC_SET_BOARD_ID: case VENDOR_CC_TPM_MODE: - case VENDOR_CC_RESET_EC: #endif /* defined(CR50_DEV) */ case EXTENSION_POST_RESET: /* Always need to reset. */ case VENDOR_CC_CCD: case VENDOR_CC_GET_BOARD_ID: - case VENDOR_CC_GET_BOOT_MODE: case VENDOR_CC_RMA_CHALLENGE_RESPONSE: case VENDOR_CC_SPI_HASH: /* Requires physical presence. */ case VENDOR_CC_TURN_UPDATE_ON: diff --git a/common/gpio.c b/common/gpio.c index b9ba93475c..2d6544bdfe 100644 --- a/common/gpio.c +++ b/common/gpio.c @@ -168,10 +168,4 @@ int gpio_get_ternary(enum gpio_signal signal) return pu && !pd ? 2 : pd; } -__attribute__((weak)) void gpio_set_wakepin(enum gpio_signal signal, - uint32_t flags) -{ - /* Some chips may need their own implementations */ -} - /*****************************************************************************/ diff --git a/common/gpio_commands.c b/common/gpio_commands.c index d922ad5891..32bd896c0c 100644 --- a/common/gpio_commands.c +++ b/common/gpio_commands.c @@ -9,7 +9,6 @@ #include "console.h" #include "gpio.h" #include "host_command.h" -#include "printf.h" #include "system.h" #include "util.h" @@ -80,39 +79,30 @@ static enum ec_error_list set(const char *name, int value) static void print_gpio_info(int gpio) { - int changed, v; - char flags_str[33]; + int changed, v, flags; if (!gpio_is_implemented(gpio)) return; /* Skip unsupported signals */ v = gpio_get_level(gpio); #ifdef CONFIG_CMD_GPIO_EXTENDED - { - int flags; - - flags = gpio_get_flags(gpio); - snprintf(flags_str, sizeof(flags_str), - "%s%s%s%s%s%s%s%s%s%s%s", - flags & GPIO_INPUT ? "I " : "", - flags & GPIO_OUTPUT ? "O " : "", - flags & GPIO_LOW ? "L " : "", - flags & GPIO_HIGH ? "H " : "", - flags & GPIO_ANALOG ? "A " : "", - flags & GPIO_OPEN_DRAIN ? "ODR " : "", - flags & GPIO_PULL_UP ? "PU " : "", - flags & GPIO_PULL_DOWN ? "PD " : "", - flags & GPIO_ALTERNATE ? "ALT " : "", - flags & GPIO_SEL_1P8V ? "1P8 " : "", - flags & GPIO_LOCKED ? "LCK " : ""); - } + flags = gpio_get_flags(gpio); #else - flags_str[0] = 0; + flags = 0; #endif changed = last_val_changed(gpio, v); - ccprintf(" %d%c %s%s\n", v, - (changed ? '*' : ' '), flags_str, gpio_get_name(gpio)); + ccprintf(" %d%c %s%s%s%s%s%s%s%s%s%s\n", v, (changed ? '*' : ' '), + (flags & GPIO_INPUT ? "I " : ""), + (flags & GPIO_OUTPUT ? "O " : ""), + (flags & GPIO_LOW ? "L " : ""), + (flags & GPIO_HIGH ? "H " : ""), + (flags & GPIO_ANALOG ? "A " : ""), + (flags & GPIO_OPEN_DRAIN ? "ODR " : ""), + (flags & GPIO_PULL_UP ? "PU " : ""), + (flags & GPIO_PULL_DOWN ? "PD " : ""), + (flags & GPIO_ALTERNATE ? "ALT " : ""), + gpio_get_name(gpio)); /* Flush console to avoid truncating output */ cflush(); diff --git a/common/nvmem.c b/common/nvmem.c index 92e097077a..42fc0ba161 100644 --- a/common/nvmem.c +++ b/common/nvmem.c @@ -106,8 +106,11 @@ static int nvmem_save(void) rv = new_nvmem_save(); - nvmem_unlock_cache(rv == EC_SUCCESS); + if (rv == EC_SUCCESS) + nvmem_act_partition = NVMEM_NOT_INITIALIZED; + nvmem_mutex.write_in_progress = 0; + nvmem_release_cache(); return rv; } @@ -504,12 +507,3 @@ void nvmem_clear_cache(void) nvmem_save(); } - -void nvmem_unlock_cache(int init_act_partition) -{ - if (init_act_partition) - nvmem_act_partition = NVMEM_NOT_INITIALIZED; - - nvmem_mutex.write_in_progress = 0; - nvmem_release_cache(); -} diff --git a/common/system.c b/common/system.c index c24e97b93f..6267cf9683 100644 --- a/common/system.c +++ b/common/system.c @@ -21,7 +21,6 @@ #include "mpu.h" #endif #include "panic.h" -#include "shared_mem.h" #include "system.h" #include "task.h" #include "timer.h" @@ -879,19 +878,15 @@ DECLARE_CONSOLE_COMMAND(hibernate, command_hibernate, static void print_build_string(void) { const char *full_build_string; - char *p; + const char *p; char symbol; - char *next; - int index; - size_t len; int seen_colonv; ccprintf("Build: "); full_build_string = system_get_build_info(); - len = strlen(full_build_string); /* 50 characters or less, will fit into the terminal line. */ - if (len < 50) { + if (strlen(full_build_string) < 50) { ccprintf("%s\n", full_build_string); return; } @@ -901,41 +896,24 @@ static void print_build_string(void) * space (this is where the main version ends), and then on each space * after the ":v" substring, this is where subcomponent versions are * separated. - * - * To avoid invoking ccprintf() for one character at a time let's - * create a mutable copy and modify it to print in multiple lines. */ - if (shared_mem_acquire(len + 1, &p) != EC_SUCCESS) { - /* - * Should never happen, but if it does let's - * just print it in single line. - */ - ccprintf("%s\n", full_build_string); - return; - } - - memcpy(p, full_build_string, len + 1); - next = p; - index = 0; + p = full_build_string; seen_colonv = 1; - do { - symbol = next[index++]; + symbol = *p++; + while (symbol) { if ((symbol == ' ') && seen_colonv) { - next[index - 1] = '\0'; seen_colonv = 0; /* Indent each line under 'Build: ' */ - ccprintf("%s\n ", next); - next += index; - index = 0; - continue; + ccprintf("\n "); + } else { + if ((symbol == ':') && (*p == 'v')) + seen_colonv = 1; + ccprintf("%c", symbol); } - if ((symbol == ':') && (next[index] == 'v')) - seen_colonv = 1; - } while (symbol); - ccprintf("%s\n", next); - - shared_mem_release(p); + symbol = *p++; + } + ccprintf("\n"); } static int command_version(int argc, char **argv) diff --git a/common/update_fw.c b/common/update_fw.c new file mode 100644 index 0000000000..de374ec4dd --- /dev/null +++ b/common/update_fw.c @@ -0,0 +1,167 @@ +/* Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "byteorder.h" +#include "console.h" +#include "extension.h" +#include "flash.h" +#include "hooks.h" +#include "include/compile_time_macros.h" +#include "uart.h" +#include "update_fw.h" +#include "util.h" + +#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) + +/* Various update extension command return values. */ +enum return_value { + UPDATE_SUCCESS = 0, + UPDATE_BAD_ADDR = 1, + UPDATE_ERASE_FAILURE = 2, + UPDATE_DATA_ERROR = 3, + UPDATE_WRITE_FAILURE = 4, + UPDATE_VERIFY_ERROR = 5, + UPDATE_GEN_ERROR = 6, +}; + +/* + * The payload of the update command. (Integer values in network byte order). + * + * block digest: the first four bytes of the sha1 digest of the rest of the + * structure. + * block_base: address where this block needs to be written to. + * block_body: variable size data to written at address 'block_base'. + */ +struct update_command { + uint32_t block_digest; + uint32_t block_base; + uint8_t block_body[0]; +} __packed; + + +const struct section_descriptor *valid_section; + +/* Pick the section where updates can go to based on current code address. */ +static int set_valid_section(void) +{ + int i; + uint32_t run_time_offs = (uint32_t) set_valid_section - + CONFIG_PROGRAM_MEMORY_BASE; + valid_section = rw_sections; + + for (i = 0; i < num_rw_sections; i++) { + if ((run_time_offs > rw_sections[i].sect_base_offset) && + (run_time_offs < rw_sections[i].sect_top_offset)) + continue; + valid_section = rw_sections + i; + break; + } + if (i == num_rw_sections) { + CPRINTF("%s:%d No valid section found!\n", __func__, __LINE__); + return EC_ERROR_INVAL; + } + return EC_SUCCESS; +} + +/* Verify that the passed in block fits into the valid area. */ +static int valid_update_chunk(uint32_t block_offset, size_t body_size) +{ + if (valid_section && + (block_offset >= valid_section->sect_base_offset) && + ((block_offset + body_size) <= valid_section->sect_top_offset)) + return 1; + + return 0; +} + +void fw_update_command_handler(void *body, + size_t cmd_size, + size_t *response_size) +{ + struct update_command *cmd_body = body; + uint8_t *rv = body; + size_t body_size; + uint32_t block_offset; + + /* + * A single byte response, unless this is the first message in the + * programming sequence. + */ + *response_size = sizeof(*rv); + + body_size = cmd_size - offsetof(struct update_command, block_body); + if (body_size < 0) { + CPRINTF("%s:%d\n", __func__, __LINE__); + *rv = UPDATE_GEN_ERROR; + return; + } + + if (!cmd_body->block_base && !body_size) { + int ret; + /* + * This is the first message of the update process, let's + * determine the valid update section and erase its contents. + */ + ret = set_valid_section(); + if (ret) { + CPRINTF("%s:%d no valid section\n", __func__, __LINE__); + return; + } + + if (flash_physical_erase(valid_section->sect_base_offset, + valid_section->sect_top_offset - + valid_section->sect_base_offset)) { + CPRINTF("%s:%d erase failure of 0x%x..+0x%x\n", + __func__, __LINE__, + valid_section->sect_base_offset, + valid_section->sect_top_offset - + valid_section->sect_base_offset); + *rv = UPDATE_ERASE_FAILURE; + return; + } + + /* + * Successful erase means that we need to return the base + * address of the section to be programmed with the update. + */ + *(uint32_t *)body = htobe32(valid_section->sect_base_offset + + CONFIG_PROGRAM_MEMORY_BASE); + *response_size = sizeof(uint32_t); + return; + } + + /* Check if the block will fit into the valid area. */ + block_offset = be32toh(cmd_body->block_base) - + CONFIG_PROGRAM_MEMORY_BASE; + if (!valid_update_chunk(block_offset, body_size)) { + *rv = UPDATE_BAD_ADDR; + CPRINTF("%s:%d Write out of range %x ..+%d (Window %x - %x)\n", + __func__, __LINE__, + block_offset, body_size, + valid_section->sect_base_offset, + valid_section->sect_top_offset); + return; + } + + if (flash_physical_write(block_offset, body_size, + cmd_body->block_body) != EC_SUCCESS) { + *rv = UPDATE_WRITE_FAILURE; + CPRINTF("%s:%d update write error @0x%x:%x\n", + __func__, __LINE__, block_offset, body_size); + return; + } + + /* Werify that data was written properly. */ + if (memcmp(cmd_body->block_body, (void *) + (block_offset + CONFIG_PROGRAM_MEMORY_BASE), + body_size)) { + *rv = UPDATE_VERIFY_ERROR; + CPRINTF("%s:%d update verification error\n", + __func__, __LINE__); + return; + } + + *rv = UPDATE_SUCCESS; +} diff --git a/common/usb_update.c b/common/usb_update.c new file mode 100644 index 0000000000..bfc93b0925 --- /dev/null +++ b/common/usb_update.c @@ -0,0 +1,352 @@ +/* Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "byteorder.h" +#include "common.h" +#include "console.h" +#include "consumer.h" +#include "include/compile_time_macros.h" +#include "queue_policies.h" +#include "shared_mem.h" +#include "system.h" +#include "update_fw.h" +#include "usb_api.h" +#include "usb_hw.h" +#include "usb-stream.h" +#include "util.h" + +#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) + +/* + * This file is an adaptation layer between the USB interface and the firmware + * update engine. The engine expects to receive long blocks of data, 1K or so + * in size, prepended by the offset where the data needs to be programmed into + * the flash and a 4 byte integrity check value. + * + * The USB transfer, on the other hand, operates on much shorter chunks of + * data, typically 64 bytes in this case. This module reassembles firmware + * programming blocks from the USB chunks, and invokes the programmer passing + * it the full block. + * + * The programmer reports results by putting the return value of one or four + * bytes into the same buffer where the block was passed in. This wrapper + * retrieves the programmer's return value, normalizes it to 4 bytes and sends + * it back to the host. + * + * In the end of the successful image transfer and programming, the host send + * the reset command, and the device reboots itself. + */ + +struct consumer const update_consumer; +struct usb_stream_config const usb_update; + +static struct queue const update_to_usb = QUEUE_DIRECT(64, uint8_t, + null_producer, + usb_update.consumer); +static struct queue const usb_to_update = QUEUE_DIRECT(64, uint8_t, + usb_update.producer, + update_consumer); + +USB_STREAM_CONFIG_FULL(usb_update, + USB_IFACE_UPDATE, + USB_CLASS_VENDOR_SPEC, + USB_SUBCLASS_GOOGLE_UPDATE, + USB_PROTOCOL_GOOGLE_UPDATE, + USB_STR_UPDATE_NAME, + USB_EP_UPDATE, + USB_MAX_PACKET_SIZE, + USB_MAX_PACKET_SIZE, + usb_to_update, + update_to_usb) + + +/* The receiver can be in one of the states below. */ +enum rx_state { + rx_idle, /* Nothing happened yet. */ + rx_inside_block, /* Assembling a block to pass to the programmer. */ + rx_outside_block, /* Waiting for the next block to start or for the + reset command. */ + rx_awaiting_reset /* Waiting for reset confirmation. */ +}; + +/* This is the format of the header the programmer expects. */ +struct update_command { + uint32_t block_digest; /* first 4 bytes of sha1 of the rest of the + block. */ + uint32_t block_base; /* Offset of this block into the flash SPI. */ +}; + +/* This is the format of the header the host uses. */ +struct update_pdu_header { + uint32_t block_size; /* Total size of the block, including this + field. */ + union { + struct update_command cmd; + uint32_t resp; /* The programmer puts response to the same + buffer where the command was. */ + }; + /* The actual payload goes here. */ +}; + +enum rx_state rx_state_ = rx_idle; +static uint8_t *block_buffer; +static uint32_t block_size; +static uint32_t block_index; + +/* + * Verify that the contens of the USB rx queue is a valid transfer start + * message from host, and if so - save its contents in the passed in + * update_pdu_header structure. + */ +static int valid_transfer_start(struct consumer const *consumer, size_t count, + struct update_pdu_header *pupdu) +{ + int i; + + /* + * Let's just make sure we drain the queue no matter what the contents + * are. This way they won't be in the way during next callback, even + * if these contents are not what's expected. + */ + i = count; + while (i > 0) { + QUEUE_REMOVE_UNITS(consumer->queue, pupdu, + MIN(i, sizeof(*pupdu))); + i -= sizeof(*pupdu); + } + + if (count != sizeof(struct update_pdu_header)) { + CPRINTS("FW update: wrong first block, size %d", count); + return 0; + } + + /* In the first block the payload (updu.cmd) must be all zeros. */ + for (i = 0; i < sizeof(pupdu->cmd); i++) + if (((uint8_t *)&pupdu->cmd)[i]) + return 0; + return 1; +} + +/* + * When was last time a USB callback was called, in microseconds, free running + * timer. + */ +static uint64_t prev_activity_timestamp; + +#define UPDATE_PROTOCOL_VERSION 2 + +/* Called to deal with data from the host */ +static void update_out_handler(struct consumer const *consumer, size_t count) +{ + struct update_pdu_header updu; + size_t resp_size; + uint32_t resp_value; + uint64_t delta_time; + + /* How much time since the previous USB callback? */ + delta_time = get_time().val - prev_activity_timestamp; + prev_activity_timestamp += delta_time; + + /* If timeout exceeds 5 seconds - let's start over. */ + if ((delta_time > 5000000) && (rx_state_ != rx_idle)) { + if (block_buffer) { + /* + * Previous transfer could have been aborted mid + * block. + */ + shared_mem_release(block_buffer); + block_buffer = NULL; + } + rx_state_ = rx_idle; + CPRINTS("FW update: recovering after timeout"); + } + + if (rx_state_ == rx_idle) { + /* + * When responding to the very first packet of the update + * sequence, the original implementation was responding with a + * four byte value, just as to any other block of the transfer + * sequence. + * + * It became clear that there is a need to be able to enhance + * the update protocol, while stayng backwards compatible. To + * achieve that we respond to the very first packet with an 8 + * byte value, the first 4 bytes the same as before, the + * second 4 bytes - the protocol version number. + * + * This way if on the host side receiving of a four byte value + * in response to the first packet is an indication of the + * 'legacy' protocol, version 0. Receiving of an 8 byte + * response would communicate the protocol version in the + * second 4 bytes. + */ + struct { + uint32_t value; + uint32_t version; + } startup_resp; + + if (!valid_transfer_start(consumer, count, &updu)) + return; + + CPRINTS("FW update: starting..."); + + fw_update_command_handler(&updu.cmd, count - + offsetof(struct update_pdu_header, + cmd), + &resp_size); + + if (resp_size == 4) { + /* Already in network order. */ + startup_resp.value = updu.resp; + rx_state_ = rx_outside_block; + } else { + /* This must be a single byte error code. */ + startup_resp.value = htobe32(*((uint8_t *)&updu.resp)); + } + + startup_resp.version = htobe32(UPDATE_PROTOCOL_VERSION); + + /* Let the host know what updater had to say. */ + QUEUE_ADD_UNITS(&update_to_usb, &startup_resp, + sizeof(startup_resp)); + return; + } + + if (rx_state_ == rx_awaiting_reset) { + /* + * Any USB data received in this state triggers reset, no + * response required. + */ + CPRINTS("reboot hard"); + cflush(); + system_reset(SYSTEM_RESET_HARD); + while (1) + ; + } + + if (rx_state_ == rx_outside_block) { + /* + * Expecting to receive the beginning of the block or the + * reset command if all data blocks have been processed. + */ + if (count == 4) { + uint32_t command; + + QUEUE_REMOVE_UNITS(consumer->queue, &command, + sizeof(command)); + command = be32toh(command); + if (command == UPDATE_DONE) { + CPRINTS("FW update: done"); + resp_value = 0; + QUEUE_ADD_UNITS(&update_to_usb, &resp_value, + sizeof(resp_value)); + rx_state_ = rx_awaiting_reset; + return; + } else { + CPRINTS("Unexpected packet command 0x%x", + command); + } + } + + /* + * At this point we expect a block start message. It is + * sizeof(updu) bytes in size, but is not the transfer start + * message, which also is of that size AND has the command + * field of all zeros. + */ + if (valid_transfer_start(consumer, count, &updu) || + (count != sizeof(updu))) + /* + * Instead of a block start message we received either + * a transfer start message or a chunk. We must have + * gotten out of sync with the host. + */ + return; + + /* Let's allocate a large enough buffer. */ + block_size = be32toh(updu.block_size) - + offsetof(struct update_pdu_header, cmd); + if (shared_mem_acquire(block_size, (char **)&block_buffer) + != EC_SUCCESS) { + /* TODO:(vbendeb) report out of memory here. */ + CPRINTS("FW update: error: failed to alloc %d bytes.", + block_size); + return; + } + + /* + * Copy the rest of the message into the block buffer to pass + * to the updater. + */ + block_index = sizeof(updu) - + offsetof(struct update_pdu_header, cmd); + memcpy(block_buffer, &updu.cmd, block_index); + block_size -= block_index; + rx_state_ = rx_inside_block; + return; + } + + /* Must be inside block. */ + QUEUE_REMOVE_UNITS(consumer->queue, block_buffer + block_index, count); + block_index += count; + block_size -= count; + + if (block_size) { + if (count == sizeof(updu)) { + /* + * A block header size instead of chunk size message + * has been received. There must have been some packet + * loss and the host is restarting this block. + * + * Let's copy its contents into the header structure. + */ + memcpy(&updu, block_buffer + block_index - count, + count); + + + /* And re-allocate a large enough buffer. */ + shared_mem_release(block_buffer); + block_size = be32toh(updu.block_size) - + offsetof(struct update_pdu_header, cmd); + if (shared_mem_acquire(block_size, + (char **)&block_buffer) + != EC_SUCCESS) { + /* TODO:(vbendeb) report out of memory here. */ + CPRINTS("FW update: error: failed to alloc " + "%d bytes.", block_size); + return; + } + + /* + * Copy the rest of the message into the block buffer + * to pass to the updater. + */ + block_index = sizeof(updu) - + offsetof(struct update_pdu_header, cmd); + memcpy(block_buffer, &updu.cmd, block_index); + block_size -= block_index; + } + return; /* More to come. */ + } + + /* + * Ok, the entire block has been received and reassembled, pass it to + * the updater for verification and programming. + */ + fw_update_command_handler(block_buffer, block_index, &resp_size); + + resp_value = block_buffer[0]; + QUEUE_ADD_UNITS(&update_to_usb, &resp_value, sizeof(resp_value)); + rx_state_ = rx_outside_block; + shared_mem_release(block_buffer); + block_buffer = NULL; +} + +struct consumer const update_consumer = { + .queue = &usb_to_update, + .ops = &((struct consumer_ops const) { + .written = update_out_handler, + }), +}; diff --git a/include/common.h b/include/common.h index 793e1244ae..48c4a46172 100644 --- a/include/common.h +++ b/include/common.h @@ -225,8 +225,6 @@ enum ec_error_list { /* Verified boot data errors */ EC_ERROR_VBOOT_DATA = 0x1200, EC_ERROR_VBOOT_DATA_VERIFY = 0x1201, - EC_ERROR_VBOOT_DATA_INCOMPATIBLE = 0x1202, - EC_ERROR_VBOOT_DATA_UNDERSIZED = 0x1203, /* Module-internal error codes may use this range. */ EC_ERROR_INTERNAL_FIRST = 0x10000, diff --git a/include/config.h b/include/config.h index 02968bea47..049a83edc8 100644 --- a/include/config.h +++ b/include/config.h @@ -861,11 +861,6 @@ #define CONFIG_CONSOLE_VERBOSE /* - * Enable EC-CR50 communication (a.k.a. EC-EFS2). This is for CR50 config only. - */ -#undef CONFIG_EC_EFS_SUPPORT - -/* * Enable the experimental console. * * NOTE: If you enable this experimental console, you will need to run the @@ -2707,9 +2702,6 @@ /* Enable USB serial console module. */ #undef CONFIG_USB_CONSOLE -/* Require explicit enable call vs. active at time zero. */ -#undef CONFIG_USB_CONSOLE_DEFAULT_DISABLED - /* * Enable USB serial console module using usb stream config. * NOTE: CONFIG_USB_CONSOLE and CONFIG_USB_CONSOLE_STREAM should be defined @@ -2726,6 +2718,9 @@ /* Support USB HID interface. */ #undef CONFIG_USB_HID +/* Support USB HID keyboard interface. */ +#undef CONFIG_USB_HID_KEYBOARD + /* Support USB HID touchpad interface. */ #undef CONFIG_USB_HID_TOUCHPAD @@ -2961,6 +2956,11 @@ /* Firmware updates using other than HC channel(s). */ #undef CONFIG_NON_HC_FW_UPDATE #undef CONFIG_USB_FW_UPDATE +/* A different config for the same update. TODO(vbendeb): dedup these */ +#undef CONFIG_USB_UPDATE + +/* Add support for pairing over the USB update interface. */ +#undef CONFIG_USB_PAIRING /* PDU size for fw update over USB (or TPM). */ #define CONFIG_UPDATE_PDU_SIZE 1024 diff --git a/include/ec_comm.h b/include/ec_comm.h deleted file mode 100644 index dd4d105d4a..0000000000 --- a/include/ec_comm.h +++ /dev/null @@ -1,52 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_COMM_H -#define __CROS_EC_COMM_H -#include <stdint.h> -#include "common.h" -/* GPIO Interrupt handler for GPIO_EC_PACKET_MODE_EN rising edge */ -void ec_comm_packet_mode_en(enum gpio_signal unsed); -/* GPIO Interrupt handler for GPIO_EC_PACKET_MODE_DIS falling edge */ -void ec_comm_packet_mode_dis(enum gpio_signal unsed); -/* - * Return True if the given UART is in packet mode, in which EC-CR50 - * communication is on-going. - */ -int ec_comm_is_uart_in_packet_mode(int uart); -/* - * Try to process the given char as a EC-CR50 communication packet. - * If EC-CR50 communication is broken or uninitiated yet, then - * it does not process it. - * - * @return 1 if the given char was detected and processed as a part of packet. - * 0 otherwise. - */ -int ec_comm_process_packet(uint8_t ch); -/* - * Block or unblock EC-CR50 communication. - * @param block non-zero value blocks EC-CR50 communication. - * Zero value unblocks it. - */ -void ec_comm_block(int block); -/* Reset EC EFS context */ -void ec_efs_reset(void); -/* Set EC-EFS boot_mode */ -uint16_t ec_efs_set_boot_mode(const char *data, const uint8_t size); -/* Verify the given hash data against the EC-FW hash from kernel secdata */ -uint16_t ec_efs_verify_hash(const char *hash_data, const uint8_t size); - -/* Re-load EC Hash code from TPM Kernel Secdata */ -void ec_efs_refresh(void); -/* print EC-EFS status */ -void ec_efs_print_status(void); -/* corrupt ECRW hash */ -enum ec_error_list ec_efs_corrupt_hash(void); - -#ifdef BOARD_HOST -/* return the current boot mode. For test purpose only. */ -uint8_t ec_efs_get_boot_mode(void); -#endif - -#endif /* __CROS_EC_COMM_H */ diff --git a/include/gpio.h b/include/gpio.h index c09673e8b6..1d6bc4c091 100644 --- a/include/gpio.h +++ b/include/gpio.h @@ -32,13 +32,7 @@ #define GPIO_SEL_1P8V BIT(16) /* Support 1.8v */ #define GPIO_ALTERNATE BIT(17) /* GPIO used for alternate function. */ #define GPIO_LOCKED BIT(18) /* Lock GPIO output and configuration */ -#define GPIO_HIB_WAKE_HIGH BIT(19) /* Hibernate wake on high level */ -#define GPIO_HIB_WAKE_LOW BIT(20) /* Hibernate wake on low level */ -#define GPIO_HIB_WAKE_RISING BIT(21) /* Hibernate wake on rising edge */ -#define GPIO_HIB_WAKE_FALLING BIT(22) /* Hibernate wake on falling edge */ -#ifdef CONFIG_GPIO_POWER_DOWN -#define GPIO_POWER_DOWN BIT(23) /* Pin and pad is powered off */ -#endif +#define GPIO_HIB_WAKE_HIGH BIT(19) /* Hibernate wake on high level */ /* Common flag combinations */ #define GPIO_OUT_LOW (GPIO_OUTPUT | GPIO_LOW) @@ -54,8 +48,6 @@ #define GPIO_INT_LEVEL (GPIO_INT_LOW | GPIO_INT_HIGH) #define GPIO_INT_ANY (GPIO_INT_BOTH | GPIO_INT_LEVEL) #define GPIO_INT_BOTH_DSLEEP (GPIO_INT_BOTH | GPIO_INT_DSLEEP) -#define GPIO_HIB_WAKE_MASK (GPIO_HIB_WAKE_HIGH | GPIO_HIB_WAKE_LOW | \ - GPIO_HIB_WAKE_RISING|GPIO_HIB_WAKE_FALLING) /* Convert GPIO mask to GPIO number / index. */ #define GPIO_MASK_TO_NUM(mask) (__fls(mask)) @@ -278,15 +270,4 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags); */ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func); -/** - * Configure a GPIO as wake source on a given condition and enable it, or - * disable it. - * - * @param signal GPIO to enable to wake Cr50 up - * @param flags Wake condition. Should be one among - * GPIO_HIB_WAKE_{HIGH, LOW, RISING, FALLING} to enable it - * as a wake pin. 0 to disable it. - */ -void gpio_set_wakepin(enum gpio_signal signal, uint32_t flags); - #endif /* __CROS_EC_GPIO_H */ diff --git a/include/hooks.h b/include/hooks.h index 5b2efdb668..66e6484521 100644 --- a/include/hooks.h +++ b/include/hooks.h @@ -48,16 +48,7 @@ enum hook_priority { HOOK_PRIO_INIT_VBOOT_HASH = HOOK_PRIO_FIRST + 11, /* Init charge manager before usage in board init */ HOOK_PRIO_CHARGE_MANAGER_INIT = HOOK_PRIO_FIRST + 12, - /* - * Priorities for CR50 modules. - * HOOK_PRIO_INIT_CR50_BOARD is for board_init() in board/cr50/board.c - * which calls nvmem_init(). - * ec_efs_init() should not be called prior to board_init(). - * ec_comm_init() should not be called prior to ec_efs_init(). - */ - HOOK_PRIO_INIT_CR50_BOARD = HOOK_PRIO_DEFAULT, - HOOK_PRIO_INIT_EC_EFS = HOOK_PRIO_INIT_CR50_BOARD + 1, - HOOK_PRIO_INIT_EC_CR50_COMM = HOOK_PRIO_INIT_EC_EFS + 1, + /* Specific values to lump temperature-related hooks together */ HOOK_PRIO_TEMP_SENSOR = 6000, /* After all sensors have been polled */ diff --git a/include/nvmem.h b/include/nvmem.h index 77a488ea5b..b9eda700cf 100644 --- a/include/nvmem.h +++ b/include/nvmem.h @@ -210,18 +210,10 @@ void *nvmem_cache_base(enum nvmem_users user); */ void nvmem_clear_cache(void); -void nvmem_wipe_cache(void); - -/* - * Unlock nvmem mutex lock. - * - * @param init_act_partition: boolean to request to initialize active nvmem - * partition status or not. - */ -void nvmem_unlock_cache(int init_act_partition); - #ifdef __cplusplus } #endif +void nvmem_wipe_cache(void); + #endif /* __CROS_EC_NVMEM_UTILS_H */ diff --git a/include/system.h b/include/system.h index 42ef3b9b4a..8890100875 100644 --- a/include/system.h +++ b/include/system.h @@ -379,7 +379,6 @@ enum { */ SLEEP_MASK_JTAG = BIT(16), /* JTAG is in use. */ SLEEP_MASK_CONSOLE = BIT(17), /* Console is in use. */ - SLEEP_MASK_EC_CR50_COMM = BIT(18), /* EC-CR50 commncation is active. */ SLEEP_MASK_FORCE_NO_LOW_SPEED = BIT(31) /* Force disable. */ }; diff --git a/include/test_util.h b/include/test_util.h index 99b4c0cf81..23f89b8adb 100644 --- a/include/test_util.h +++ b/include/test_util.h @@ -175,11 +175,6 @@ void test_chipset_on(void); /* Simulates chipset power off */ void test_chipset_off(void); -/* Start/stop capturing a specific UART output */ -void test_capture_uartn(int uart, int enabled); -/* Get captured a specific UART output */ -const char *test_get_captured_uartn(int uart); - /* Start/stop capturing console output */ void test_capture_console(int enabled); diff --git a/include/tpm_nvmem.h b/include/tpm_nvmem.h index 3315148323..2508c9ae65 100644 --- a/include/tpm_nvmem.h +++ b/include/tpm_nvmem.h @@ -8,7 +8,6 @@ #define __CROS_EC_TPM_NVMEM_H #define FIRMWARE_NV_INDEX 0x1007 -#define KERNEL_NV_INDEX 0x1008 -#define FWMP_NV_INDEX 0x100a +#define FWMP_NV_INDEX 0x100a #endif /* __CROS_EC_TPM_NVMEM_H */ diff --git a/include/tpm_vendor_cmds.h b/include/tpm_vendor_cmds.h index 8eff2fad5d..c1295d7fb5 100644 --- a/include/tpm_vendor_cmds.h +++ b/include/tpm_vendor_cmds.h @@ -142,10 +142,6 @@ enum vendor_cmd_cc { VENDOR_CC_TRNG_TEST = 51, - /* EC EFS(Early Firmware Selection) commands */ - VENDOR_CC_GET_BOOT_MODE = 52, - VENDOR_CC_RESET_EC = 53, - LAST_VENDOR_COMMAND = 65535, }; diff --git a/include/vboot.h b/include/vboot.h deleted file mode 100644 index ba924508c7..0000000000 --- a/include/vboot.h +++ /dev/null @@ -1,145 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_INCLUDE_VBOOT_H -#define __CROS_EC_INCLUDE_VBOOT_H - -#include "common.h" -#include "vb21_struct.h" -#include "rsa.h" -#include "sha256.h" - -#define CR50_COMM_VERSION 0x00 -#define CR50_COMM_PREAMBLE 0xec -#define MIN_LENGTH_PREAMBLE 4 -#define CR50_COMM_MAGIC_CHAR0 'E' -#define CR50_COMM_MAGIC_CHAR1 'C' -#define CR50_COMM_MAGIC_WORD ((CR50_COMM_MAGIC_CHAR1 << 8) | \ - CR50_COMM_MAGIC_CHAR0) - -/* - * EC-Cr50 data stream looks like as follows: - * - * [preamble][header][payload] - * - * preamble: CR50_COMM_PREAMBLE (at least MIN_LENGTH_PREAMBLE times) - * header: struct cr50_comm_packet - * payload: data[] - */ -struct cr50_comm_packet { - /* Header */ - uint16_t magic; /* CR50_COMM_MAGIC_WORD */ - uint8_t version;/* Struct version. 4MSB=Major. 4LSB=Minor. */ - uint8_t crc; /* checksum computed from all bytes after crc */ - uint16_t cmd; /* CR50_COMM_CMD_* if EC sends */ - /* CR50_COMM_RESPONSE(X) if CR50 sends. */ - uint8_t size; /* Size of 'data[]' member. */ - uint8_t data[]; /* Payload */ -} __packed; - -#define CR50_COMM_MAX_DATA_SIZE 32 -#define CR50_COMM_MAX_PACKET_SIZE (sizeof(struct cr50_comm_packet) + \ - CR50_COMM_MAX_DATA_SIZE) - -/* EC-CR50 commands (2 bytes) for cr50_comm_packet.cmd */ -#define CR50_COMM_CMD_SET_BOOT_MODE 0x0001 -#define CR50_COMM_CMD_VERIFY_HASH 0x0002 - -/* EC-CR50 response codes (2 bytes) for cr50_comm_packet.cmd */ -#define CR50_COMM_RESPONSE(X) ((CR50_COMM_PREAMBLE << 8) | \ - ((X) & 0xff)) -#define CR50_COMM_SUCCESS CR50_COMM_RESPONSE(0x00) -#define CR50_COMM_ERROR_UNKNOWN CR50_COMM_RESPONSE(0x01) -#define CR50_COMM_ERROR_MAGIC CR50_COMM_RESPONSE(0x02) -#define CR50_COMM_ERROR_CRC CR50_COMM_RESPONSE(0x03) -#define CR50_COMM_ERROR_SIZE CR50_COMM_RESPONSE(0x04) -#define CR50_COMM_ERROR_TIMEOUT CR50_COMM_RESPONSE(0x05) -#define CR50_COMM_ERROR_UNDEFINED_CMD CR50_COMM_RESPONSE(0x06) -#define CR50_COMM_ERROR_BAD_PAYLOAD CR50_COMM_RESPONSE(0x07) -#define CR50_COMM_ERROR_STRUCT_VERSION CR50_COMM_RESPONSE(0x08) -#define CR50_COMM_ERROR_NVMEM CR50_COMM_RESPONSE(0x09) - -/* - * BIT(0) : NO_BOOT flag - * BIT(1) : RECOVERY flag - */ -enum ec_efs_boot_mode { - EC_EFS_BOOT_MODE_NORMAL = 0x00, - EC_EFS_BOOT_MODE_NO_BOOT = 0x01, - - /* boot_mode is uint8_t */ - EC_EFS_BOOT_MODE_LIMIT = 255, -}; - -/**************************************************************************** - * This is quoted from 2secdata_struct.h in the directory, - * src/platform/vboot_reference/firmware/2lib/include/. - ****************************************************************************/ - -/* Kernel secure storage space */ -#define VB2_SECDATA_KERNEL_STRUCT_VERSION_MIN 0x10 -#define VB2_SECDATA_KERNEL_UID 0x4752574c /* 'LWRG' */ -struct vb2_secdata_kernel { - uint8_t struct_version; /* top-half:major. bottom-half:minor. */ - uint8_t struct_size; /* Whole structure size */ - uint8_t crc8; /* CRC for everything below */ - uint8_t reserved0; - - uint32_t kernel_versions; /* Kernel versions */ - uint8_t ec_hash[SHA256_DIGEST_SIZE]; -} __packed; - -/** - * Validate key contents. - * - * @param key - * @return EC_SUCCESS or EC_ERROR_* - */ -int vb21_is_packed_key_valid(const struct vb21_packed_key *key); - -/** - * Validate signature contents. - * - * @param sig Signature to be validated. - * @param key Key to be used for validating <sig>. - * @return EC_SUCCESS or EC_ERROR_* - */ -int vb21_is_signature_valid(const struct vb21_signature *sig, - const struct vb21_packed_key *key); - -/** - * Check data region is filled with ones - * - * @param data Data to be validated. - * @param start Offset where validation starts. - * @param end Offset where validation ends. data[end] won't be checked. - * @return EC_SUCCESS or EC_ERROR_* - */ -int vboot_is_padding_valid(const uint8_t *data, uint32_t start, uint32_t end); - -/** - * Verify data by RSA signature - * - * @param data Data to be verified. - * @param len Number of bytes in <data>. - * @param key Key to be used for verification. - * @param sig Signature of <data> - * @return EC_SUCCESS or EC_ERROR_* - */ -int vboot_verify(const uint8_t *data, int len, - const struct rsa_public_key *key, const uint8_t *sig); - -/** - * Entry point of EC EFS - */ -void vboot_main(void); - -/** - * Get if vboot requires PD comm to be enabled or not - * - * @return 1: need PD communication. 0: PD communication is not needed. - */ -int vboot_need_pd_comm(void); - -#endif /* __CROS_EC_INCLUDE_VBOOT_H */ diff --git a/test/build.mk b/test/build.mk index db2a1eab0f..e279fae70f 100644 --- a/test/build.mk +++ b/test/build.mk @@ -31,7 +31,6 @@ else test-list-host = base32 test-list-host += console_edit test-list-host += crc32 -test-list-host += ec_comm test-list-host += extpwr_gpio test-list-host += flash test-list-host += flash_log @@ -64,7 +63,6 @@ charge_manager_drp_charging-y=charge_manager.o charge_ramp-y+=charge_ramp.o console_edit-y=console_edit.o crc32-y=crc32.o -ec_comm-y=ec_comm.o extpwr_gpio-y=extpwr_gpio.o fan-y=fan.o flash-y=flash.o diff --git a/test/ec_comm.c b/test/ec_comm.c deleted file mode 100644 index ba92e3132d..0000000000 --- a/test/ec_comm.c +++ /dev/null @@ -1,374 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Test ec_comm - */ - -#include "common.h" -#include "crc8.h" -#include "ec_comm.h" -#include "test_util.h" -#include "timer.h" -#include "tpm_nvmem.h" -#include "tpm_nvmem_ops.h" -#include "uart.h" -#include "util.h" -#include "vboot.h" - -const uint8_t sample_ec_hash[SHA256_DIGEST_SIZE] = { - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, - 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, -}; - -struct vb2_secdata_kernel test_secdata = { - .struct_version = VB2_SECDATA_KERNEL_STRUCT_VERSION_MIN, - .struct_size = sizeof(struct vb2_secdata_kernel), - .reserved0 = 0, - .kernel_versions = VB2_SECDATA_KERNEL_UID, -}; - -union cr50_test_packet { - struct cr50_comm_packet ph; - uint8_t packet[CR50_COMM_MAX_PACKET_SIZE * 2]; -}; - -union cr50_test_packet sample_packet_cmd_set_mode = { - .ph.magic = CR50_COMM_MAGIC_WORD, - .ph.version = CR50_COMM_VERSION, - .ph.crc = 0, - .ph.cmd = CR50_COMM_CMD_SET_BOOT_MODE, - .ph.size = 1, -}; - -union cr50_test_packet sample_packet_cmd_verify_hash = { - .ph.magic = CR50_COMM_MAGIC_WORD, - .ph.version = CR50_COMM_VERSION, - .ph.crc = 0, - .ph.cmd = CR50_COMM_CMD_VERIFY_HASH, - .ph.size = SHA256_DIGEST_SIZE, -}; - -/* EC Reset Count. It is used to see if ec has been reset. */ -static int ec_reset_count_; - -/* - * Return 1 if EC has been reset since the last call of this function, or - * 0 otherwise. - */ -static int ec_has_reset(void) -{ - static int prev_ec_reset_count; - - if (prev_ec_reset_count == ec_reset_count_) - return 0; - - prev_ec_reset_count = ec_reset_count_; - return 1; -} - -void board_reboot_ec_deferred(int usec_delay_used) -{ - /* ec_reset */ - ec_reset_count_++; - ec_efs_reset(); -} - -enum tpm_read_rv read_tpm_nvmem(uint16_t object_index, uint16_t object_size, - void *obj_value) -{ - /* Check the input parameter */ - if (object_index != KERNEL_NV_INDEX) - return TPM_READ_NOT_FOUND; - if (object_size != test_secdata.struct_size) - return TPM_READ_TOO_SMALL; - - /* - * Copy the test_secdata to obj_value as if it was loaded - * from NVMEM. - */ - memcpy(obj_value, (void *)&test_secdata, object_size); - - return TPM_READ_SUCCESS; -} - -/* - * Return 1 if the byte is found in buf string. - * 0 otherwise - */ -static int find_byte(const char *buf, uint8_t byte) -{ - int i = strlen(buf); - - while (i--) { - if (*buf == byte) - return 1; - buf++; - } - return 0; -} - -/* - * Calculate CRC8 of the the given CR50 packet and fill it in - * the packet. - */ -static void calculate_crc8(union cr50_test_packet *pk) -{ - const int offset_cmd = offsetof(struct cr50_comm_packet, cmd); - - /* Calculate the sample EC-CR50 packet. */ - pk->ph.crc = crc8((uint8_t *)&pk->ph.cmd, - (sizeof(struct cr50_comm_packet) - + pk->ph.size - offset_cmd)); -} - -/* - * Test EC CR50 communication with the given EC-CR50 packet. - * - * @param pk an ec_cr50 comm packet to test - * @param preambles the number of preambles - * @param resp_exp the expected response in two bytes as in - * CR50_COMM_RESPONSE. - * if it is zero, then no response is expected. - */ -static int test_ec_comm(const union cr50_test_packet *pk, int preambles, - uint16_t resp_exp) -{ - uint8_t *buf; - int leng; - int i; - const char *resp; - - leng = sizeof(struct cr50_comm_packet) + pk->ph.size; - - /* Prepare the input packet. */ - buf = (uint8_t *)pk; - - /* Start the test */ - ec_comm_packet_mode_en(1); - TEST_ASSERT(ec_comm_is_uart_in_packet_mode(UART_EC)); - - for (i = 0; i < preambles; i++) - ec_comm_process_packet(CR50_COMM_PREAMBLE); - - test_capture_uartn(UART_EC, 1); - - for (i = 0; i < leng; i++) - ec_comm_process_packet(buf[i]); - - resp = test_get_captured_uartn(UART_EC); - - if (resp_exp) - TEST_ASSERT(*(uint16_t *)resp == resp_exp); - else - /* Check if there was any EC-CR50-comm response. */ - TEST_ASSERT(find_byte(resp, '\xec') == 0); - - test_capture_uartn(UART_EC, 0); - - ec_comm_packet_mode_dis(1); - TEST_ASSERT(!ec_comm_is_uart_in_packet_mode(UART_EC)); - - return EC_SUCCESS; -} - -/* - * Test the failure case for packet errors. - */ -static int test_ec_comm_packet_failure(void) -{ - /* Copy the sample packet to buffer. */ - union cr50_test_packet pk = sample_packet_cmd_verify_hash; - int preambles = MIN_LENGTH_PREAMBLE; - - ec_has_reset(); - - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NORMAL); - - /* Test 1: Test with less preambles than required. */ - calculate_crc8(&pk); - TEST_ASSERT(!test_ec_comm(&pk, 1, 0)); - - /* Test 2: Test a wrong magic */ - pk.ph.magic = 0x1234; - calculate_crc8(&pk); - TEST_ASSERT(!test_ec_comm(&pk, preambles, CR50_COMM_ERROR_MAGIC)); - - /* Test 3: Test with a wrong CRC */ - pk = sample_packet_cmd_verify_hash; - calculate_crc8(&pk); - pk.ph.crc += 0x01; /* corrupt the CRC */ - TEST_ASSERT(!test_ec_comm(&pk, preambles, CR50_COMM_ERROR_CRC)); - - /* Test 4: Test with too large payload */ - pk = sample_packet_cmd_verify_hash; - pk.ph.size = SHA256_DIGEST_SIZE + 1; - pk.ph.data[SHA256_DIGEST_SIZE] = 0xff; - calculate_crc8(&pk); - - TEST_ASSERT(!test_ec_comm(&pk, preambles, CR50_COMM_ERROR_SIZE)); - - /* Test 5: Test with a undefined command */ - pk = sample_packet_cmd_verify_hash; - pk.ph.cmd = 0x1000; - calculate_crc8(&pk); - TEST_ASSERT(!test_ec_comm(&pk, preambles, - CR50_COMM_ERROR_UNDEFINED_CMD)); - - /* Test 6: Test with a wrong struct version */ - pk = sample_packet_cmd_verify_hash; - pk.ph.version = CR50_COMM_VERSION + 0x01; - calculate_crc8(&pk); - TEST_ASSERT(!test_ec_comm(&pk, preambles, - CR50_COMM_ERROR_STRUCT_VERSION)); - - /* Check if ec has ever been reset during these tests */ - TEST_ASSERT(!ec_has_reset()); - - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NORMAL); - - return EC_SUCCESS; -} - -/* - * Test cases for set_boot_mode command. - */ -static int test_ec_comm_set_boot_mode(void) -{ - /* Copy the sample packet to buffer. */ - union cr50_test_packet pk = sample_packet_cmd_set_mode; - int preambles; - - ec_has_reset(); - - /* Test 1: Attempt to set boot mode to NORMAL. */ - pk.ph.data[0] = EC_EFS_BOOT_MODE_NORMAL; - calculate_crc8(&pk); - preambles = MIN_LENGTH_PREAMBLE * 2; - TEST_ASSERT(!test_ec_comm(&pk, preambles, CR50_COMM_SUCCESS)); - TEST_ASSERT(!ec_has_reset()); /* EC must not be reset. */ - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NORMAL); - - /* Test 2: Attempt to set boot mode to NORMAL again. */ - preambles = MIN_LENGTH_PREAMBLE; - TEST_ASSERT(!test_ec_comm(&pk, preambles, CR50_COMM_SUCCESS)); - TEST_ASSERT(!ec_has_reset()); /* EC must not be reset. */ - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NORMAL); - - /* - * Test 3: Attempt to set boot mode to NO BOOT. - * EC should not be reset with this boot mode change from NORMAL - * to NO_BOOT. - */ - pk.ph.data[0] = EC_EFS_BOOT_MODE_NO_BOOT; - calculate_crc8(&pk); - TEST_ASSERT(!test_ec_comm(&pk, preambles, CR50_COMM_SUCCESS)); - TEST_ASSERT(!ec_has_reset()); /* EC must not be reset. */ - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NO_BOOT); - - /* - * Test 4: Attempt to set boot mode to NO BOOT again. - * EC should not be reset since it is a repeating command. - */ - TEST_ASSERT(!test_ec_comm(&pk, preambles, CR50_COMM_SUCCESS)); - TEST_ASSERT(!ec_has_reset()); /* EC must not be reset. */ - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NO_BOOT); - - /* - * Test 5: Attempt to set boot mode to NORMAL. - * EC should be reset with this boot mode change from NO_BOOT - * to NORMAL. - */ - pk.ph.data[0] = EC_EFS_BOOT_MODE_NORMAL; - calculate_crc8(&pk); - TEST_ASSERT(!test_ec_comm(&pk, preambles, 0)); - TEST_ASSERT(ec_has_reset()); /* EC must be reset. */ - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NORMAL); - - return EC_SUCCESS; -} - -/* - * Test cases for verify_hash command. - */ -static int test_ec_comm_verify_hash(void) -{ - /* Copy the sample packet to buffer. */ - union cr50_test_packet pk = sample_packet_cmd_verify_hash; - int preambles = MIN_LENGTH_PREAMBLE; - - ec_has_reset(); - - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NORMAL); - - /* Test 1: Attempt to verify EC Hash. */ - calculate_crc8(&pk); - preambles = MIN_LENGTH_PREAMBLE * 2; - TEST_ASSERT(!test_ec_comm(&pk, preambles, CR50_COMM_SUCCESS)); - TEST_ASSERT(!ec_has_reset()); - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NORMAL); - - /* Test 2: Attempt to verify EC Hash again. */ - preambles = MIN_LENGTH_PREAMBLE; - TEST_ASSERT(!test_ec_comm(&pk, preambles, CR50_COMM_SUCCESS)); - TEST_ASSERT(!ec_has_reset()); - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NORMAL); - - /* Test 3: Attempt to verify a wrong EC Hash. */ - pk.ph.data[0] ^= 0xff; /* corrupt the payload */ - calculate_crc8(&pk); - TEST_ASSERT(!test_ec_comm(&pk, preambles, CR50_COMM_ERROR_BAD_PAYLOAD)); - TEST_ASSERT(!ec_has_reset()); /* EC should not be reset though. */ - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NO_BOOT); - - /* Test 4: Attempt to verify a wrong EC Hash again. */ - TEST_ASSERT(!test_ec_comm(&pk, preambles, CR50_COMM_ERROR_BAD_PAYLOAD)); - TEST_ASSERT(!ec_has_reset()); /* EC should not be reset though. */ - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NO_BOOT); - - /* - * Test 5: Attempt to verify the correct EC Hash. - * EC should be reset because EC Boot mode is NO BOOT. - */ - pk = sample_packet_cmd_verify_hash; - calculate_crc8(&pk); - preambles = MIN_LENGTH_PREAMBLE * 2; - TEST_ASSERT(!test_ec_comm(&pk, preambles, 0)); - TEST_ASSERT(ec_has_reset()); /* EC must be reset. */ - TEST_ASSERT(ec_efs_get_boot_mode() == EC_EFS_BOOT_MODE_NORMAL); - - /* Check if ec has ever been reset during these tests */ - return EC_SUCCESS; -} - -void run_test(void) -{ - uint8_t size_to_crc; - - /* Prepare the sample kernel secdata and a sample packet. */ - memcpy(test_secdata.ec_hash, sample_ec_hash, sizeof(sample_ec_hash)); - memcpy(sample_packet_cmd_verify_hash.ph.data, - sample_ec_hash, sizeof(sample_ec_hash)); - - /* Calculate the CRC8 for the sample kernel secdata. */ - size_to_crc = test_secdata.struct_size - - offsetof(struct vb2_secdata_kernel, crc8) - - sizeof(test_secdata.crc8); - test_secdata.crc8 = crc8((uint8_t *)&test_secdata.reserved0, - size_to_crc); - - /* Module init */ - board_reboot_ec_deferred(0); - ec_efs_refresh(); - - /* Start test */ - test_reset(); - - RUN_TEST(test_ec_comm_packet_failure); - RUN_TEST(test_ec_comm_set_boot_mode); - RUN_TEST(test_ec_comm_verify_hash); - - test_print_result(); -} diff --git a/test/ec_comm.tasklist b/test/ec_comm.tasklist deleted file mode 100644 index 52c0d390ef..0000000000 --- a/test/ec_comm.tasklist +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * See CONFIG_TASK_LIST in config.h for details. - */ -#define CONFIG_TEST_TASK_LIST /* No test task */ diff --git a/test/test_config.h b/test/test_config.h index f382dce53c..9a9632e838 100644 --- a/test/test_config.h +++ b/test/test_config.h @@ -208,11 +208,6 @@ int ncp15wb_calculate_temp(uint16_t adc); #define CONFIG_USB_PD_PORT_COUNT 2 #endif -#ifdef TEST_EC_COMM -#define CONFIG_CRC8 -#define CONFIG_EC_EFS_SUPPORT -#endif - #if defined(TEST_NVMEM) || defined(TEST_NVMEM_VARS) #define CONFIG_CRC8 #define CONFIG_FLASH_ERASED_VALUE32 (-1U) diff --git a/util/signer/ec_RW-manifest-dev.json b/util/signer/ec_RW-manifest-dev.json index 48cbdafe1e..a99bd639a9 100644 --- a/util/signer/ec_RW-manifest-dev.json +++ b/util/signer/ec_RW-manifest-dev.json @@ -39,8 +39,8 @@ "timestamp": 0, "epoch": 0, // FWR diversification contributor, 32 bits. - "major": 5, // FW2_HIK_CHAIN counter. - "minor": 1, // Mostly harmless version field. + "major": 3, // FW2_HIK_CHAIN counter. + "minor": 26, // Mostly harmless version field. "applysec": -1, // Mask to and with fuse BROM_APPLYSEC. "config1": 13, // Which BROM_CONFIG1 actions to take before launching. "err_response": 0, // Mask to or with fuse BROM_ERR_RESPONSE. diff --git a/util/signer/ec_RW-manifest-prod.json b/util/signer/ec_RW-manifest-prod.json index 99bf79d989..ce63cfcf01 100644 --- a/util/signer/ec_RW-manifest-prod.json +++ b/util/signer/ec_RW-manifest-prod.json @@ -46,8 +46,8 @@ // epoch/major/minor would be preferred "timestamp": 1, "epoch": 0, // FWR diversification contributor, 32 bits. - "major": 5, // FW2_HIK_CHAIN counter. - "minor": 1, // Mostly harmless version field. + "major": 3, // FW2_HIK_CHAIN counter. + "minor": 26, // Mostly harmless version field. "applysec": -1, // Mask to and with fuse BROM_APPLYSEC. "config1": 13, // Which BROM_CONFIG1 actions to take before launching. "err_response": 0, // Mask to or with fuse BROM_ERR_RESPONSE. |