diff options
author | Scott Collyer <scollyer@google.com> | 2019-04-23 14:32:38 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2019-04-25 00:59:36 -0700 |
commit | 1386656117173f506b42deb0ce5be713703366ad (patch) | |
tree | 6b2e2f6004652cb57d2f309b7cb09290d9d63ff7 | |
parent | cf02f0076fbc0afbde2394fd05ce097c33aaffdb (diff) | |
download | chrome-ec-1386656117173f506b42deb0ce5be713703366ad.tar.gz |
hatch: Make PP5000_A_PGOOD a power signal interrupt
This signal is of the power signals, but it had been set as just a
GPIO_INPPUT. This CL corrects and makes in a interrupt signal similar
to the other power sequencing signals.
BUG=b:129372306
BRANCH=none
TEST=Verify that Hatch system boots successfully.
Change-Id: Id4434cbd41ad1cc8996f2759d5a0f5698e74918c
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1579900
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
-rw-r--r-- | board/hatch/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/hatch/gpio.inc b/board/hatch/gpio.inc index 28a7d400f7..9911e3d093 100644 --- a/board/hatch/gpio.inc +++ b/board/hatch/gpio.inc @@ -22,6 +22,7 @@ GPIO_INT(SLP_S4_L, PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt) #endif GPIO_INT(PG_EC_RSMRST_L, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(PG_EC_ALL_SYS_PWRGD, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PP5000_A_PG_OD, PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt) /* Sensor Interrupts */ GPIO_INT(BASE_SIXAXIS_INT_L, PIN(5, 6), GPIO_INT_FALLING, bmi160_interrupt) @@ -51,7 +52,6 @@ GPIO(EN_PP5000_A_V0, PIN(7, 3), GPIO_DEFAULT) GPIO(EN_A_RAILS, PIN(A, 3), GPIO_OUT_LOW) GPIO(EC_PCH_RSMRST_L, PIN(A, 6), GPIO_OUT_LOW) GPIO(EC_PROCHOT_ODL, PIN(6, 3), GPIO_ODR_HIGH) -GPIO(PP5000_A_PG_OD, PIN(D, 7), GPIO_INPUT) GPIO(EC_PCH_SYS_PWROK, PIN(3, 7), GPIO_OUT_LOW) GPIO(CPU_C10_GATE_L, PIN(6, 7), GPIO_INPUT) |