diff options
| author | jongpil19.jung <jongpil19.jung@samsung.com> | 2015-09-13 00:14:30 +0900 |
|---|---|---|
| committer | ChromeOS bot <3su6n15k.default@developer.gserviceaccount.com> | 2015-09-16 00:27:15 +0000 |
| commit | 8f759333fe65db3d934645577ae5946421460c8b (patch) | |
| tree | 4df9783737c2d0c92abbf4b1fb0690747121fdfd | |
| parent | 58f1a61e36541ab4fe7c140a6160366ebed1b9fa (diff) | |
| download | chrome-ec-8f759333fe65db3d934645577ae5946421460c8b.tar.gz | |
Celes: EC support GD25Q41B for external EC ROM.
MEC1322 use external spi rom. Now, we support W25X40 and W25Q64.
Celes will use GD25Q41B for external EC ROM.
So, we need to add define for GD25Q41B for Celes.
BUG=chrome-os-partner:45246
BRANCH=firmware-strago-7287.B
TEST=emerge-celes chromeos-ec
flashrom -p ec --wp-range 0x00020000 0x00020000
flashrom -p ec --wp-eanble
reboot
flashrom -p ec --wp-status
Change-Id: I24ce990ca579c12ff69f64932cb1b2b013f38824
Signed-off-by: jongpil19.jung <jongpil19.jung@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/299570
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | board/celes/board.h | 2 | ||||
| -rw-r--r-- | common/spi_flash_reg.c | 2 | ||||
| -rw-r--r-- | include/config.h | 3 | ||||
| -rw-r--r-- | include/spi_flash_reg.h | 2 |
4 files changed, 6 insertions, 3 deletions
diff --git a/board/celes/board.h b/board/celes/board.h index 5dadeeab9a..961a05ec28 100644 --- a/board/celes/board.h +++ b/board/celes/board.h @@ -35,7 +35,7 @@ #define CONFIG_SPI_CS_GPIO GPIO_PVT_CS0 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_SIZE 524288 -#define CONFIG_SPI_FLASH_W25Q64 +#define CONFIG_SPI_FLASH_GD25Q41B #define CONFIG_USB_PORT_POWER_SMART #define CONFIG_USB_PORT_POWER_SMART_SIMPLE diff --git a/common/spi_flash_reg.c b/common/spi_flash_reg.c index 6eab99f1cc..9ee814bbe3 100644 --- a/common/spi_flash_reg.c +++ b/common/spi_flash_reg.c @@ -37,7 +37,7 @@ struct protect_range { * none or half of the ROM. The table is searched sequentially, so ordering * according to likely configurations improves performance slightly. */ -#ifdef CONFIG_SPI_FLASH_W25X40 +#if defined(CONFIG_SPI_FLASH_W25X40) || defined(CONFIG_SPI_FLASH_GD25Q41B) static const struct protect_range spi_flash_protect_ranges[] = { { X, X, X, { 0, 0, 0 }, 0, 0 }, /* No protection */ { X, X, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */ diff --git a/include/config.h b/include/config.h index 2418c0da69..bce186ff9b 100644 --- a/include/config.h +++ b/include/config.h @@ -1347,6 +1347,9 @@ /* Support W25X40 SPI flash */ #undef CONFIG_SPI_FLASH_W25X40 +/* Support GD25Q41B SPI flash */ +#undef CONFIG_SPI_FLASH_GD25Q41B + /* SPI flash part supports SR2 register */ #undef CONFIG_SPI_FLASH_HAS_SR2 diff --git a/include/spi_flash_reg.h b/include/spi_flash_reg.h index e8d9144a6f..e42d9baa99 100644 --- a/include/spi_flash_reg.h +++ b/include/spi_flash_reg.h @@ -34,7 +34,7 @@ /* SR2 register existence based upon chip */ #ifdef CONFIG_SPI_FLASH_W25X40 #undef CONFIG_SPI_FLASH_HAS_SR2 -#elif defined(CONFIG_SPI_FLASH_W25Q64) +#elif defined(CONFIG_SPI_FLASH_W25Q64) || defined(CONFIG_SPI_FLASH_GD25Q41B) #define CONFIG_SPI_FLASH_HAS_SR2 #endif |