zephyr: mchp: Add mec1727 board specific configuration

Add mec1727 board specific configuration

BUG=none
BRANCH=main
TEST=zmake testall

Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: Ia39f959329d7be86b926fa8017a1f6527523ed69
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3606923
Reviewed-by: Yuval Peress <peress@google.com>

5 files changed, 347 insertions, 0 deletions

diff --git a/zephyr/boards/arm/mec1727/Kconfig.board b/zephyr/boards/arm/mec1727/Kconfig.board
new file mode 100644
index 0000000000..66a3993185
--- /dev/null
+++ b/zephyr/boards/arm/mec1727/Kconfig.board
@@ -0,0 +1,15 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# "BOARD" below refers to a Zephyr board, which does not have a 1:1
+# mapping with the Chrome OS concept of a board.  By Zephyr's
+# conventions, we'll still call it "BOARD_*" to make this more
+# applicable to be upstreamed, even though this code is shared by all
+# projects using the MEC172x EVB board.
+config BOARD_MEC1727
+	bool "MEC1727 Zephyr Board"
+	depends on SOC_MEC172X_NSZ
+	# MCHP XEC doesn't actually have enough ram for coverage, but this will
+	# allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/mec1727/Kconfig.defconfig b/zephyr/boards/arm/mec1727/Kconfig.defconfig
new file mode 100644
index 0000000000..0708bda48c
--- /dev/null
+++ b/zephyr/boards/arm/mec1727/Kconfig.defconfig
@@ -0,0 +1,35 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if BOARD_MEC1727
+
+config BOARD
+	default "mec1727"
+
+# Zephyr internal stack sizes
+
+config IDLE_STACK_SIZE
+	default 400
+
+config SYSTEM_WORKQUEUE_STACK_SIZE
+	default 1024
+
+# Chromium EC stack sizes
+
+config TASK_CHARGER_STACK_SIZE
+	default 1056
+
+config TASK_KEYSCAN_STACK_SIZE
+	default 1024
+
+config TASK_PD_STACK_SIZE
+	default 1184
+
+config TASK_PD_INT_STACK_SIZE
+	default 1024
+
+config TASK_USB_CHG_STACK_SIZE
+	default 1024
+
+endif # BOARD_MEC1727
diff --git a/zephyr/boards/arm/mec1727/board.cmake b/zephyr/boards/arm/mec1727/board.cmake
new file mode 100644
index 0000000000..b67f47c819
--- /dev/null
+++ b/zephyr/boards/arm/mec1727/board.cmake
@@ -0,0 +1,5 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(MCHP_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.mchp.bin)
diff --git a/zephyr/boards/arm/mec1727/mec1727.dts b/zephyr/boards/arm/mec1727/mec1727.dts
new file mode 100644
index 0000000000..c88e61b692
--- /dev/null
+++ b/zephyr/boards/arm/mec1727/mec1727.dts
@@ -0,0 +1,235 @@
+/* Copyright 2022 Microchip Technology Inc. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/microchip/mec1727.dtsi>
+#include <cros/thermistor/thermistor.dtsi>
+#include <dt-bindings/gpio_defines.h>
+#include <microchip/mec172xnsz.dtsi>
+#include <microchip/mec172x/mec172xnsz-pinctrl.dtsi>
+
+/ {
+	model = "MEC1727";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &int_flash;
+	};
+
+	pinmux: pinmux {
+		compatible = "microchip,xec-pinmux";
+
+		pinmux_000_036: pinmux-0 {
+			ph-reg = <&gpio_000_036>;
+			port-num = <0>;
+		};
+		pinmux_040_076: pinmux-1 {
+			ph-reg = <&gpio_040_076>;
+			port-num = <1>;
+		};
+		pinmux_100_136: pinmux-2 {
+			ph-reg = <&gpio_100_136>;
+			port-num = <2>;
+		};
+		pinmux_140_176: pinmux-3 {
+			ph-reg = <&gpio_140_176>;
+			port-num = <3>;
+		};
+		pinmux_200_236: pinmux-4 {
+			ph-reg = <&gpio_200_236>;
+			port-num = <4>;
+		};
+		pinmux_240_276: pinmux-5 {
+			ph-reg = <&gpio_240_276>;
+			port-num = <5>;
+		};
+	};
+
+	named-pwms {
+		compatible = "named-pwms";
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ddr_soc: ddr_soc {
+			label = "TEMP_DDR_SOC";
+			enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC";
+			io-channels = <&adc0 5>;
+		};
+		adc_ambient: ambient {
+			label = "TEMP_AMBIENT";
+			enum-name = "ADC_TEMP_SENSOR_2_AMBIENT";
+			io-channels = <&adc0 3>;
+		};
+		adc_charger: charger {
+			label = "TEMP_CHARGER";
+			enum-name = "ADC_TEMP_SENSOR_3_CHARGER";
+			io-channels = <&adc0 0>;
+		};
+		adc_wwan: wwan {
+			label = "TEMP_WWAN";
+			enum-name = "ADC_TEMP_SENSOR_4_WWAN";
+			io-channels = <&adc0 4>;
+		};
+	};
+
+	soc {
+		/delete-node/ rtc@400f5000;
+		/delete-node/ kscan@40009c00;
+
+		crtc: cros-rtc@400f5000 {
+			compatible = "microchip,xec-cros-rtc";
+			reg = <0x400f5000 0x100>;
+			interrupts = <119 0>, <120 0>;
+			label = "CRTC";
+		};
+
+		cros_kb_raw: cros-kb-raw@40009c00 {
+			compatible = "microchip,xec-cros-kb-raw";
+			reg = <0x40009c00 0x18>;
+			label = "CROS_KB_RAW_0";
+			interrupts = <135 0>;
+		};
+	};
+};
+
+&cpu0 {
+	status = "okay";
+/* cpu-power-states = <&suspend_to_idle_instant &suspend_to_idle_normal>; */
+};
+
+&bbram {
+	status = "okay";
+};
+
+&ecia {
+	status = "okay";
+};
+
+/* Enable aggregated GIRQ24/25 for eSPI virtual wires */
+&girq24 {
+	status = "okay";
+};
+
+&girq25 {
+	status = "okay";
+};
+
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_reset_n_gpio061
+		     &espi_cs_n_gpio066
+		     &espi_clk_gpio065
+		     &espi_io0_gpio070
+		     &espi_io1_gpio071
+		     &espi_io2_gpio072
+		     &espi_io3_gpio073>;
+	pinctrl-names = "default";
+};
+
+/* Host facing devices on eSPI bus */
+&kbc0 {
+	status = "okay";
+};
+
+&acpi_ec0 {
+	status = "okay";
+};
+
+&acpi_ec1 {
+	status = "okay";
+};
+
+&emi0 {
+	status = "okay";
+};
+
+&p80bd0 {
+	status = "okay";
+};
+
+&crtc {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_tx_gpio104 &uart0_rx_gpio105>;
+	pinctrl-names = "default";
+};
+
+&spi0 {
+	status = "okay";
+	clock-frequency = <12000000>;
+	lines = <2>;
+	port-sel = <2>;
+	chip-select = <0>;
+	pinctrl-0 = < &gpspi_cs_n_gpio116
+		      &gpspi_clk_gpio117
+		      &gpspi_io0_gpio074
+		      &gpspi_io1_gpio075
+		      &gpspi_wp_n_gpio076 >;
+	pinctrl-names = "default";
+
+	int_flash: sst25pf040@0 {
+		compatible ="jedec,spi-nor";
+		/*  4194304 bits = 512K Bytes */
+		size = <0x400000>;
+		label = "SST25PF040";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+		status = "okay";
+		jedec-id = [62 06 13];
+	};
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/*
+	 * No KSO2 (It's inverted and implemented by GPIO for
+	 * CONFIG_KEYBOARD_COL2_INVERTED.)
+	 */
+	pinctrl-0 = <&ksi0_gpio017
+		     &ksi1_gpio020
+			 &ksi2_gpio021
+		     &ksi3_gpio026
+		     &ksi4_gpio027
+		     &ksi5_gpio030
+		     &ksi6_gpio031
+		     &ksi7_gpio032
+		     &kso00_gpio040
+		     &kso01_gpio045
+		     &kso03_gpio047
+		     &kso04_gpio107
+		     &kso05_gpio112
+		     &kso06_gpio113
+		     &kso07_gpio120
+		     &kso08_gpio121
+		     &kso09_gpio122
+		     &kso10_gpio123
+		     &kso11_gpio124
+		     &kso12_gpio125>;
+	pinctrl-names = "default";
+};
+
+/* Chrome design: KSI02 to H1 has not pull-up resistor */
+&ksi2_gpio021 {
+	bias-pull-up;
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc00_gpio200
+		     &adc03_gpio203
+		     &adc04_gpio204
+		     &adc05_gpio205>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/boards/arm/mec1727/mec1727_defconfig b/zephyr/boards/arm/mec1727/mec1727_defconfig
new file mode 100644
index 0000000000..69f0ff53f5
--- /dev/null
+++ b/zephyr/boards/arm/mec1727/mec1727_defconfig
@@ -0,0 +1,57 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_MEC172X=y
+
+# Platform Configuration
+CONFIG_SOC_MEC172X_NSZ=y
+CONFIG_BOARD_MEC1727=y
+CONFIG_RTOS_TIMER=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinmux Driver
+CONFIG_PINMUX=y
+
+# Pinctrl Driver
+CONFIG_PINCTRL=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+CONFIG_WDT_XEC=y
+
+# Power Management
+#CONFIG_PM=y
+#CONFIG_PM_POLICY_APP=y
+#CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
+
+# BBRAM
+CONFIG_BBRAM=y
+CONFIG_BBRAM_XEC=y
+
+# SPI
+CONFIG_SPI=y
+# MCHP build config error CONFIG_SPI_FLASH=y
+
+# Flash
+CONFIG_FLASH=y
+CONFIG_SPI_NOR=y
+# disabling this causes build error: calling function to read JEDEC ID
+# MEC1727 internal SST25PF040 does not support SFDP
+CONFIG_FLASH_JESD216_API=y