diff options
| author | Jett Rink <jettrink@chromium.org> | 2020-02-20 10:31:51 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-02-25 02:28:20 +0000 |
| commit | 4e6b1019d5e507710c4b4662656959bb9c767e8f (patch) | |
| tree | dbc7486c5aa0a97b3e4357fa4ad57e97400d685a | |
| parent | 7a9b2d8a7c83c087e40ddd9461408490b80ae400 (diff) | |
| download | chrome-ec-4e6b1019d5e507710c4b4662656959bb9c767e8f.tar.gz | |
cleanup: tab over register values
Tab over register values underneath the register definition for
consistent style.
BRANCH=none
BUG=none
TEST=none
Change-Id: I823a454fc57d4ee455c9efb693baff8838bc7d3c
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2067158
Reviewed-by: Diana Z <dzigterman@chromium.org>
| -rw-r--r-- | chip/stm32/registers.h | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 5926dda278..e6b89fb315 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -66,15 +66,15 @@ REG32(STM32_TIM_BASE(n) + (offset)) #define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00) -#define STM32_TIM_CR1_CEN BIT(0) +#define STM32_TIM_CR1_CEN BIT(0) #define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04) #define STM32_TIM_SMCR(n) STM32_TIM_REG(n, 0x08) #define STM32_TIM_DIER(n) STM32_TIM_REG(n, 0x0C) #define STM32_TIM_SR(n) STM32_TIM_REG(n, 0x10) #define STM32_TIM_EGR(n) STM32_TIM_REG(n, 0x14) -#define STM32_TIM_EGR_UG BIT(0) +#define STM32_TIM_EGR_UG BIT(0) #define STM32_TIM_CCMR1(n) STM32_TIM_REG(n, 0x18) -#define STM32_TIM_CCMR1_OC1PE BIT(2) +#define STM32_TIM_CCMR1_OC1PE BIT(2) /* Use in place of TIM_CCMR1_OC1M_0 through 2 from STM documentation. */ #define STM32_TIM_CCMR1_OC1M(n) (((n) & 0x7) << 4) #define STM32_TIM_CCMR1_OC1M_MASK STM32_TIM_CCMR1_OC1M(~0) @@ -98,7 +98,7 @@ #define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C) #define STM32_TIM_CCR4(n) STM32_TIM_REG(n, 0x40) #define STM32_TIM_BDTR(n) STM32_TIM_REG(n, 0x44) -#define STM32_TIM_BDTR_MOE BIT(15) +#define STM32_TIM_BDTR_MOE BIT(15) #define STM32_TIM_DCR(n) STM32_TIM_REG(n, 0x48) #define STM32_TIM_DMAR(n) STM32_TIM_REG(n, 0x4C) #define STM32_TIM_OR(n) STM32_TIM_REG(n, 0x50) @@ -147,20 +147,20 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_LPTIM_ISR(n) STM32_LPTIM_REG(n, 0x00) #define STM32_LPTIM_ICR(n) STM32_LPTIM_REG(n, 0x04) #define STM32_LPTIM_IER(n) STM32_LPTIM_REG(n, 0x08) -#define STM32_LPTIM_INT_DOWN BIT(6) -#define STM32_LPTIM_INT_UP BIT(5) -#define STM32_LPTIM_INT_ARROK BIT(4) -#define STM32_LPTIM_INT_CMPOK BIT(3) -#define STM32_LPTIM_INT_EXTTRIG BIT(2) -#define STM32_LPTIM_INT_ARRM BIT(1) -#define STM32_LPTIM_INT_CMPM BIT(0) +#define STM32_LPTIM_INT_DOWN BIT(6) +#define STM32_LPTIM_INT_UP BIT(5) +#define STM32_LPTIM_INT_ARROK BIT(4) +#define STM32_LPTIM_INT_CMPOK BIT(3) +#define STM32_LPTIM_INT_EXTTRIG BIT(2) +#define STM32_LPTIM_INT_ARRM BIT(1) +#define STM32_LPTIM_INT_CMPM BIT(0) #define STM32_LPTIM_CFGR(n) STM32_LPTIM_REG(n, 0x0C) #define STM32_LPTIM_CR(n) STM32_LPTIM_REG(n, 0x10) -#define STM32_LPTIM_CR_RSTARE BIT(4) -#define STM32_LPTIM_CR_COUNTRST BIT(3) -#define STM32_LPTIM_CR_CNTSTRT BIT(2) -#define STM32_LPTIM_CR_SNGSTRT BIT(1) -#define STM32_LPTIM_CR_ENABLE BIT(0) +#define STM32_LPTIM_CR_RSTARE BIT(4) +#define STM32_LPTIM_CR_COUNTRST BIT(3) +#define STM32_LPTIM_CR_CNTSTRT BIT(2) +#define STM32_LPTIM_CR_SNGSTRT BIT(1) +#define STM32_LPTIM_CR_ENABLE BIT(0) #define STM32_LPTIM_CMP(n) STM32_LPTIM_REG(n, 0x14) #define STM32_LPTIM_ARR(n) STM32_LPTIM_REG(n, 0x18) #define STM32_LPTIM_CNT(n) STM32_LPTIM_REG(n, 0x1C) @@ -442,11 +442,11 @@ typedef volatile struct timer_ctlr timer_ctlr_t; /* --- TRNG --- */ #define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) #define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_SR_DRDY BIT(0) #define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ |