diff options
author | Duncan Laurie <dlaurie@google.com> | 2017-08-16 16:35:01 +0000 |
---|---|---|
committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2017-08-16 16:45:34 +0000 |
commit | 54f9b14d7f71373cb653466146c4d715123fed6c (patch) | |
tree | 52006d0662fd97b4a2cb850d07cc809f1098ddcc | |
parent | 202a0044b170a4886331cb93214cab84033c24da (diff) | |
download | chrome-ec-54f9b14d7f71373cb653466146c4d715123fed6c.tar.gz |
Revert "npcx: workaround the bug that SHM data read via eSPI may be corrupted"
This reverts commit 9271f4ca437095420506ee7e1971b3f95abc11ca.
Reason for revert: Appears to be causing issues.
BUG=b:64730183
TEST=none
Original change's description:
> npcx: workaround the bug that SHM data read via eSPI may be corrupted
>
> In eSPI systems, when the Host performs a data read from the Shared
> Memory space, the returned data may be corrupted. This is a result of
> the Core-to-Host access enable bit being toggled (by toggling CSAE bit
> in SIBCTRL register) during an eSPI transaction.
>
> The workaround in this CL is to set CSAE bit to 1 during initialization
> and remove the toggling of CSAE bit from other EC firmware code.
> (i.e., let the CSAE bit be always 1.)
>
> BRANCH=none
> BUG=none
> TEST=No build errors for make buildall. Flash poppy ec image, make sure
> it can boot to OS. Run "ectool version" over 100000 times, no error
> occurs.
>
> Change-Id: I905d8c193378e6fdd03dd944d4734611e93091d4
> Signed-off-by: Duncan Laurie <dlaurie@google.com>
> Original-Commit-Id: ddbfe690e294e595c6ed3511dcf417410d9b2804
> Original-Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe
> Original-Signed-off-by: CHLin <CHLIN56@nuvoton.com>
> Original-Reviewed-on: https://chromium-review.googlesource.com/590396
> Original-Commit-Ready: Shawn N <shawnn@chromium.org>
> Original-Tested-by: CH Lin <chlin56@nuvoton.com>
> Original-Reviewed-by: Shawn N <shawnn@chromium.org>
> Reviewed-on: https://chromium-review.googlesource.com/604726
Bug: none
Change-Id: I7fe3842fac1cad76bcc4d8f21430dd8b8ca63e5d
Reviewed-on: https://chromium-review.googlesource.com/617242
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Commit-Queue: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Trybot-Ready: Duncan Laurie <dlaurie@google.com>
-rw-r--r-- | chip/npcx/lpc.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index d1f7d48f8a..fb3b240895 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -370,6 +370,8 @@ uint8_t lpc_sib_read_kbc_reg(uint8_t io_offset) /* Lock host keyboard module */ SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKHIKBD); + /* Enable Core-to-Host Modules Access */ + SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE); /* Verify Core read/write to host modules is not in progress */ lpc_sib_wait_host_read_done(); lpc_sib_wait_host_write_done(); @@ -388,6 +390,8 @@ uint8_t lpc_sib_read_kbc_reg(uint8_t io_offset) /* Disable Core access to keyboard module */ CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_HIKBDAE); + /* Disable Core-to-Host Modules Access */ + CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE); /* unlock host keyboard module */ CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKHIKBD); @@ -722,6 +726,8 @@ void lpc_sib_write_reg(uint8_t io_offset, uint8_t index_value, /* Lock host CFG module */ SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG); + /* Enable Core-to-Host Modules Access */ + SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE); /* Enable Core access to CFG module */ SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE); /* Verify Core read/write to host modules is not in progress */ @@ -744,6 +750,8 @@ void lpc_sib_write_reg(uint8_t io_offset, uint8_t index_value, /* Disable Core access to CFG module */ CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE); + /* Disable Core-to-Host Modules Access */ + CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE); /* unlock host CFG module */ CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG); @@ -760,6 +768,8 @@ uint8_t lpc_sib_read_reg(uint8_t io_offset, uint8_t index_value) /* Lock host CFG module */ SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG); + /* Enable Core-to-Host Modules Access */ + SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE); /* Enable Core access to CFG module */ SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE); /* Verify Core read/write to host modules is not in progress */ @@ -784,6 +794,8 @@ uint8_t lpc_sib_read_reg(uint8_t io_offset, uint8_t index_value) /* Disable Core access to CFG module */ CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE); + /* Disable Core-to-Host Modules Access */ + CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE); /* unlock host CFG module */ CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG); @@ -796,9 +808,6 @@ uint8_t lpc_sib_read_reg(uint8_t io_offset, uint8_t index_value) /* For LPC host register initial via SIB module */ void host_register_init(void) { - /* Enable Core-to-Host Modules Access */ - SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE); - /* enable ACPI*/ lpc_sib_write_reg(SIO_OFFSET, 0x07, 0x11); lpc_sib_write_reg(SIO_OFFSET, 0x30, 0x01); |