diff options
| author | Gwendal Grignou <gwendal@chromium.org> | 2018-12-12 14:50:27 -0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2019-02-13 18:05:14 +0000 |
| commit | 941b02187bde22ef543b7634e067fb806830bffc (patch) | |
| tree | 3528ed428b56dabf9ea6c397eaa372f2ec724c03 | |
| parent | a422595349ff48e6f4a353895b7c3e0ef92dd858 (diff) | |
| download | chrome-ec-941b02187bde22ef543b7634e067fb806830bffc.tar.gz | |
npcx: use window index 1 and 2 instead of 0 and 1
Nuvoton specification list shared memory windows starting at index 1,
instead of the usual 0. Change code to match the spec.
BUG=none
BRANCH=master, eve-campfire
TEST=load, ectool version works.
Change-Id: If06a9402d973648ff1dfe64c5235a52d6be2aa8f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/1377572
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Gwendal Grignou <gwendal@google.com>
| -rw-r--r-- | chip/npcx/lpc.c | 16 | ||||
| -rw-r--r-- | chip/npcx/registers.h | 19 |
2 files changed, 20 insertions, 15 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 1c843420dd..b971bdbdad 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -685,14 +685,14 @@ static void lpc_sysjump(void) lpc_task_disable_irq(); /* Disable protect for Win 1 and 2. */ - NPCX_WIN_WR_PROT(0) = 0; NPCX_WIN_WR_PROT(1) = 0; - NPCX_WIN_RD_PROT(0) = 0; + NPCX_WIN_WR_PROT(2) = 0; NPCX_WIN_RD_PROT(1) = 0; + NPCX_WIN_RD_PROT(2) = 0; /* Reset base address for Win 1 and 2. */ - NPCX_WIN_BASE(0) = 0xfffffff8; NPCX_WIN_BASE(1) = 0xfffffff8; + NPCX_WIN_BASE(2) = 0xfffffff8; system_add_jump_tag(LPC_SYSJUMP_TAG, 1, sizeof(event_mask), event_mask); @@ -982,16 +982,16 @@ static void lpc_init(void) /* Semaphore and Indirect access disable */ NPCX_SHCFG = 0xE0; /* Disable Protect Win1&2*/ - NPCX_WIN_WR_PROT(0) = 0; NPCX_WIN_WR_PROT(1) = 0; - NPCX_WIN_RD_PROT(0) = 0; + NPCX_WIN_WR_PROT(2) = 0; NPCX_WIN_RD_PROT(1) = 0; + NPCX_WIN_RD_PROT(2) = 0; /* Open Win1 256 byte for Host CMD, Win2 256 for MEMMAP*/ NPCX_WIN_SIZE = 0x88; - NPCX_WIN_BASE(0) = (uint32_t)shm_mem_host_cmd; - NPCX_WIN_BASE(1) = (uint32_t)shm_memmap; + NPCX_WIN_BASE(1) = (uint32_t)shm_mem_host_cmd; + NPCX_WIN_BASE(2) = (uint32_t)shm_memmap; /* Write protect of Share memory */ - NPCX_WIN_WR_PROT(1) = 0xFF; + NPCX_WIN_WR_PROT(2) = 0xFF; /* We support LPC args and version 3 protocol */ *(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) = diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index f55b28370b..04e2d26d1f 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -994,17 +994,22 @@ enum NPCX_PMC_PWDWN_CTL_T { #define NPCX_SHM_CTL REG8(NPCX_SHM_BASE_ADDR + 0x002) #define NPCX_IMA_WIN_SIZE REG8(NPCX_SHM_BASE_ADDR + 0x005) #define NPCX_WIN_SIZE REG8(NPCX_SHM_BASE_ADDR + 0x007) -#define NPCX_SHAW_SEM(win) REG8(NPCX_SHM_BASE_ADDR + 0x008 + (win)) +#define NPCX_SHAW_SEM(win) \ + REG8(NPCX_SHM_BASE_ADDR + 0x008 + (win - 1)) #define NPCX_IMA_SEM REG8(NPCX_SHM_BASE_ADDR + 0x00B) #define NPCX_SHCFG REG8(NPCX_SHM_BASE_ADDR + 0x00E) -#define NPCX_WIN_WR_PROT(win) REG8(NPCX_SHM_BASE_ADDR + 0x010 + (win*2L)) -#define NPCX_WIN_RD_PROT(win) REG8(NPCX_SHM_BASE_ADDR + 0x011 + (win*2L)) +#define NPCX_WIN_WR_PROT(win) \ + REG8(NPCX_SHM_BASE_ADDR + 0x010 + ((win - 1) * 2L)) +#define NPCX_WIN_RD_PROT(win) \ + REG8(NPCX_SHM_BASE_ADDR + 0x011 + ((win - 1) * 2L)) #define NPCX_IMA_WR_PROT REG8(NPCX_SHM_BASE_ADDR + 0x016) #define NPCX_IMA_RD_PROT REG8(NPCX_SHM_BASE_ADDR + 0x017) -#define NPCX_WIN_BASE(win) REG32(NPCX_SHM_BASE_ADDR + 0x020 + (win*4L)) - -#define NPCX_PWIN_BASEI(win) REG16(NPCX_SHM_BASE_ADDR + 0x020 + (win*4L)) -#define NPCX_PWIN_SIZEI(win) REG16(NPCX_SHM_BASE_ADDR + 0x022 + (win*4L)) +#define NPCX_WIN_BASE(win) \ + REG32(NPCX_SHM_BASE_ADDR + 0x020 + ((win - 1) * 4L)) +#define NPCX_PWIN_BASEI(win) \ + REG16(NPCX_SHM_BASE_ADDR + 0x020 + ((win - 1) * 4L)) +#define NPCX_PWIN_SIZEI(win) \ + REG16(NPCX_SHM_BASE_ADDR + 0x022 + ((win - 1) * 4L)) #define NPCX_IMA_BASE REG32(NPCX_SHM_BASE_ADDR + 0x02C) #define NPCX_RST_CFG REG8(NPCX_SHM_BASE_ADDR + 0x03A) |