npcx: bypasses for SHM reading fail via eSPI and CSAE impact efficiency

In eSPI systems, when the host performs a data read from the Shared
Memory space, the returned data may be corrupted. This is a result of
the Core-to-Host access enable bit being toggled (by toggling CSAE bit
in SIBCTRL register) during an eSPI transaction. The bypass for this
symptom is to set CSAE bit to 1 during initialization and remove the
toggling of CSAE bit from other EC firmware code.

But keeping the CSAE bit at 1 forever also impacts the eSPI performance
a lots. When the core clock is stalled by sleep, deep sleep or wfi
instruction, the eSPI Peripheral Channel transaction is stalled if this
bit is set. The bypass for this symptom is to wake up the core by eSPI
peripheral channel transaction and let eSPI module handle the remaining
packet.

BRANCH=eve
BUG=b:64730183
TEST=No build errors for make buildall. Flash poppy ec image, make sure
     it can boot to OS. Run "ectool version" over 100000 times, no error
     occurs. Use following script "count=0; while :; do echo "---
     iteration --- $count"; time flashrom -p ec -r ec.bin; sleep 5;
     count=$((${count}+1)); done" to test eSPI performances over 1000
     times. No errors occur and all tests' efficiency are the same as
     removing CSAE bypass.

Change-Id: I13f184f5422ffc5cd8bda4349cd88249e509ee05
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Commit-Id: 20c3de1c36bf44822834ff0daa308499aa466b5c
Original-Change-Id: I1b9051c5a3d368a5917882d9d1c3bb00481a53ad
Original-Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Original-Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/620301
Original-Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/690174

2 files changed, 14 insertions, 12 deletions

diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c
index 981cf503dc..9c7199d983 100644
--- a/chip/npcx/clock.c
+++ b/chip/npcx/clock.c
@@ -375,6 +375,17 @@ void __idle(void)
 			SET_BIT(NPCX_PDOUT(0), 0);
 #endif
 			idle_sleep_cnt++;
+
+			/*
+			 * Using host access to make sure M4 core clock will
+			 * return when the eSPI accesses the Host modules if
+			 * CSAE bit is set. Please notice this symptom only
+			 * occurs at npcx5.
+			 */
+#if defined(CHIP_FAMILY_NPCX5)
+			/* Enable Host access wakeup */
+			SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
+#endif
 			/*
 			 * Normal idle : wait for interrupt
 			 * TODO (ML): Workaround method for wfi issue.
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index fb3b240895..d1f7d48f8a 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -370,8 +370,6 @@ uint8_t lpc_sib_read_kbc_reg(uint8_t io_offset)
 
 	/* Lock host keyboard module */
 	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKHIKBD);
-	/* Enable Core-to-Host Modules Access */
-	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
 	/* Verify Core read/write to host modules is not in progress */
 	lpc_sib_wait_host_read_done();
 	lpc_sib_wait_host_write_done();
@@ -390,8 +388,6 @@ uint8_t lpc_sib_read_kbc_reg(uint8_t io_offset)
 
 	/* Disable Core access to keyboard module */
 	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_HIKBDAE);
-	/* Disable Core-to-Host Modules Access */
-	CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
 	/* unlock host keyboard module */
 	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKHIKBD);
 
@@ -726,8 +722,6 @@ void lpc_sib_write_reg(uint8_t io_offset, uint8_t index_value,
 
 	/* Lock host CFG module */
 	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
-	/* Enable Core-to-Host Modules Access */
-	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
 	/* Enable Core access to CFG module */
 	SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
 	/* Verify Core read/write to host modules is not in progress */
@@ -750,8 +744,6 @@ void lpc_sib_write_reg(uint8_t io_offset, uint8_t index_value,
 
 	/* Disable Core access to CFG module */
 	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
-	/* Disable Core-to-Host Modules Access */
-	CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
 	/* unlock host CFG  module */
 	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
 
@@ -768,8 +760,6 @@ uint8_t lpc_sib_read_reg(uint8_t io_offset, uint8_t index_value)
 
 	/* Lock host CFG module */
 	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
-	/* Enable Core-to-Host Modules Access */
-	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
 	/* Enable Core access to CFG module */
 	SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
 	/* Verify Core read/write to host modules is not in progress */
@@ -794,8 +784,6 @@ uint8_t lpc_sib_read_reg(uint8_t io_offset, uint8_t index_value)
 
 	/* Disable Core access to CFG module */
 	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
-	/* Disable Core-to-Host Modules Access */
-	CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
 	/* unlock host CFG  module */
 	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
 
@@ -808,6 +796,9 @@ uint8_t lpc_sib_read_reg(uint8_t io_offset, uint8_t index_value)
 /* For LPC host register initial via SIB module */
 void host_register_init(void)
 {
+	/* Enable Core-to-Host Modules Access */
+	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
+
 	/* enable ACPI*/
 	lpc_sib_write_reg(SIO_OFFSET, 0x07, 0x11);
 	lpc_sib_write_reg(SIO_OFFSET, 0x30, 0x01);