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| author | Mulin Chao <mlchao@nuvoton.com> | 2017-08-31 14:01:51 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2017-09-28 11:10:08 +0000 |
| commit | bafca5ca95b13254316ed0dc79116564e634c534 (patch) | |
| tree | 8c444f3260d2b76add20b7e12bd90991892efee2 | |
| parent | a241e79de8f7d303c9ed6a0940c385d0b6a1cc33 (diff) | |
| download | chrome-ec-bafca5ca95b13254316ed0dc79116564e634c534.tar.gz | |
npcx: bypass for CSAE issue if CONFIG_LOW_POWER_IDLE is disabled
In order to prevent keeping the CSAE bit at 1 forever impacts the eSPI
performance, the npcx driver enables host access wakeup functionality
before ec enters deep sleep or wfi. But this bypass also should be added
in __idle() of core/cortex-m/task.c if CONFIG_LOW_POWER_IDLE is
disabled.
This CL also narrows the bypass only when host interface is eSPI.
BRANCH=eve
BUG=b:64730183
TEST=No build errors for make buildall. Disable CONFIG_LOW_POWER_IDLE
functionality on poppy and use following script "count=0; while :;
do echo "--- iteration --- $count"; time flashrom -p ec -r ec.bin; sleep
1; count=$((${count}+1)); done" to test eSPI performances over 300
times. No errors occur and all tests' efficiency are the same as
removing CSAE bypass.
Change-Id: Icf75a47862360638261c4881956bd03661527ac6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Commit-Id: ebe3caeb69aeaa9144701415decc3e6647df01cd
Original-Change-Id: I8b6b69e37318208c185747151c06b3e6bdfd2f4e
Original-Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/644967
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/690175
| -rw-r--r-- | chip/npcx/clock.c | 2 | ||||
| -rw-r--r-- | core/cortex-m/task.c | 12 |
2 files changed, 13 insertions, 1 deletions
diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c index 9c7199d983..6ba326645f 100644 --- a/chip/npcx/clock.c +++ b/chip/npcx/clock.c @@ -382,7 +382,7 @@ void __idle(void) * CSAE bit is set. Please notice this symptom only * occurs at npcx5. */ -#if defined(CHIP_FAMILY_NPCX5) +#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_ESPI) /* Enable Host access wakeup */ SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); #endif diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index 6b978c9d33..0435533b16 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -68,6 +68,18 @@ void __idle(void) { while (1) { #ifdef CHIP_NPCX + + /* + * Using host access to make sure M4 core clock will + * return when the eSPI accesses the Host modules if + * CSAE bit is set. Please notice this symptom only + * occurs at npcx5. + */ +#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_ESPI) + /* Enable Host access wakeup */ + SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); +#endif + /* * TODO (ML): A interrupt that occurs shortly before entering * idle mode starts getting services while the Core transitions |