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| author | Caveh Jalali <caveh@chromium.org> | 2018-02-08 14:45:16 -0800 |
|---|---|---|
| committer | Daisuke Nojiri <dnojiri@chromium.org> | 2018-02-19 10:33:13 -0800 |
| commit | 465d62dc78b2c4b6ba8b13cfe7e5599cc04a6810 (patch) | |
| tree | efc72f57d2d7781ab4ef894ee15b0c9e648d62a3 | |
| parent | 55d8fed577d5e5ab09472f55f8e43e631bff49d3 (diff) | |
| download | chrome-ec-465d62dc78b2c4b6ba8b13cfe7e5599cc04a6810.tar.gz | |
npcx: do not power down eSPI when enabled
if we're using eSPI for connectivity to the AP, we should never
power it down... powering it down just causes transient errors
on eSPI.
BUG=b:72838699
BRANCH=none
TEST=booted on meowth, no more eSPI bus errors.
Change-Id: I737a03bb745868c7e8e02ffd5607db4d2da74c30
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/910320
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
| -rw-r--r-- | chip/npcx/lpc.c | 3 | ||||
| -rw-r--r-- | chip/npcx/system.c | 12 |
2 files changed, 11 insertions, 4 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 190c80b412..fa3f8c8a29 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -868,9 +868,6 @@ static void lpc_init(void) clock_enable_peripheral(CGC_OFFSET_LPC, CGC_LPC_MASK, CGC_MODE_RUN | CGC_MODE_SLEEP); #ifdef CONFIG_ESPI - /* Enable clock for eSPI peripheral */ - clock_enable_peripheral(CGC_OFFSET_ESPI, CGC_ESPI_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); /* Initialize eSPI IP */ espi_init(); #else diff --git a/chip/npcx/system.c b/chip/npcx/system.c index b2d4c4b0c0..ffbe490c52 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -668,6 +668,8 @@ void chip_pre_init(void) void system_pre_init(void) { + uint8_t pwdwn6; + /* * Add additional initialization here * EC should be initialized in Booter @@ -683,7 +685,15 @@ void system_pre_init(void) #endif NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_4) = 0xF4; /* Skip ITIM2/1_PD */ NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5) = 0xF8; - NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6) = 0xF5; /* Skip ITIM5_PD */ + + pwdwn6 = 0x70 | + (1 << NPCX_PWDWN_CTL6_ITIM6_PD) | + (1 << NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */ +#if !defined(CONFIG_ESPI) + pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD; +#endif + NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6) = pwdwn6; + #if defined(CHIP_FAMILY_NPCX7) NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0x07; #endif |