diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2016-04-13 17:26:22 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-04-19 13:56:45 -0700 |
| commit | 50b198bcc15d0f2fc3921242f18c478a62b37ad1 (patch) | |
| tree | 24b9d42de8b3b23cd62e616b5f8ffa616eecc601 | |
| parent | 95858f385c35fbe6a95f0bad72ade9290b2a2d41 (diff) | |
| download | chrome-ec-50b198bcc15d0f2fc3921242f18c478a62b37ad1.tar.gz | |
npcx: shi: Don't enable GPIO_SHI_CS_L GPIO interrupt until S0
Prior to going to S0, GPIO_SHI_CS_L may be low, which can cause glitches
in the SHI HW unit. Enable the GPIO interrupt in S0, and disable it when
leaving S0.
BUG=chrome-os-partner:52222,chrome-os-partner:52217
BRANCH=None
TEST=Manual on kevin. Verify 'ectool version' succeeds with subsequent
kernel / ectool patches.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ie3494122c2486429d3f648ab9220daf5dd34f812
Reviewed-on: https://chromium-review.googlesource.com/338857
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
| -rw-r--r-- | board/kevin/board.h | 2 | ||||
| -rw-r--r-- | chip/npcx/shi.c | 31 |
2 files changed, 28 insertions, 5 deletions
diff --git a/board/kevin/board.h b/board/kevin/board.h index 1e955e3f99..9c046c6bc6 100644 --- a/board/kevin/board.h +++ b/board/kevin/board.h @@ -80,6 +80,8 @@ #define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */ #define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ #define NPCX_TACH_SEL2 0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */ +/* Enable SHI PU on transition to S0. Disable the PU otherwise for leakage. */ +#define NPCX_SHI_CS_PU /* Optional for testing */ #undef CONFIG_PECI diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c index 755f043abe..fcabb97798 100644 --- a/chip/npcx/shi.c +++ b/chip/npcx/shi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 The Chromium OS Authors. All rights reserved. + * Copyright 2015 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -758,15 +758,39 @@ static void shi_reset_prepare(void) /* Ready to receive */ state = SHI_STATE_READY_TO_RECV; + CPRINTF("RDY-"); } -DECLARE_HOOK(HOOK_CHIPSET_RESUME, shi_reset_prepare, HOOK_PRIO_DEFAULT); + +static void shi_enable(void) +{ + int gpio_flags; + + shi_reset_prepare(); + + /* Ensure SHI_CS_L interrupt is disabled */ + gpio_disable_interrupt(GPIO_SHI_CS_L); + + /* Enable PU, if requested */ + gpio_flags = GPIO_INPUT | GPIO_INT_F_FALLING; +#ifdef NPCX_SHI_CS_PU + gpio_flags |= GPIO_PULL_UP; +#endif + gpio_set_flags(GPIO_SHI_CS_L, gpio_flags); + + /* Enable SHI_CS_L interrupt */ + gpio_enable_interrupt(GPIO_SHI_CS_L); +} +DECLARE_HOOK(HOOK_CHIPSET_RESUME, shi_enable, HOOK_PRIO_DEFAULT); /* Disable SHI bus */ static void shi_disable(void) { state = SHI_STATE_DISABLED; + /* Disable SHI_CS_L interrupt */ + gpio_disable_interrupt(GPIO_SHI_CS_L); + /* Disable pullup and interrupts on SHI_CS_L */ gpio_set_flags(GPIO_SHI_CS_L, GPIO_INPUT); @@ -827,9 +851,6 @@ static void shi_init(void) /* Clear SHI events status register */ NPCX_EVSTAT = 0XFF; - /* Enable SHI_CS_L interrupt */ - gpio_enable_interrupt(GPIO_SHI_CS_L); - /* If chipset is already on, prepare for transactions */ #if !(DEBUG_SHI) if (chipset_in_state(CHIPSET_STATE_ON)) |