diff options
| author | Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com> | 2021-05-27 13:48:57 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-05-27 07:19:13 +0000 |
| commit | 9a30ce07ee553a753a5d0340b7743f64e340a38c (patch) | |
| tree | c6071cab5bd7bbb01f002db6adf34dd85f3a2221 | |
| parent | c805a09cb1afe04dda51a3443533f6e24a920863 (diff) | |
| download | chrome-ec-9a30ce07ee553a753a5d0340b7743f64e340a38c.tar.gz | |
chip/mt8192_scp: disalbe video hardware 4k capability
Disables 4K capability because the platform doesn't support it temporarily.
BRANCH=asurada
BUG=b:187896757
BUG=b:168868411
BUG=b:185977882
TEST=VDAtest passes on Asurada
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
Change-Id: I18211671fdfe13378affe28f201ca1ef67f4c36e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2921691
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com>
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Tested-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
| -rw-r--r-- | chip/mt8192_scp/ipi.c | 2 | ||||
| -rw-r--r-- | chip/mt8192_scp/ipi_chip.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/chip/mt8192_scp/ipi.c b/chip/mt8192_scp/ipi.c index 204a4d7170..462865be83 100644 --- a/chip/mt8192_scp/ipi.c +++ b/chip/mt8192_scp/ipi.c @@ -128,7 +128,7 @@ static void ipi_enable_deferred(void) scp_run.signaled = 1; strncpy(scp_run.fw_ver, system_get_version(EC_IMAGE_RW), SCP_FW_VERSION_LEN); - scp_run.dec_capability = VDEC_CAP_MM21 | VDEC_CAP_H264_SLICE | + scp_run.dec_capability = VCODEC_CAPABILITY_4K_DISABLED | VDEC_CAP_MM21 | VDEC_CAP_H264_SLICE | VDEC_CAP_VP8_FRAME | VDEC_CAP_VP9_FRAME; scp_run.enc_capability = VENC_CAP_4K; diff --git a/chip/mt8192_scp/ipi_chip.h b/chip/mt8192_scp/ipi_chip.h index abd1ab77b4..6067517328 100644 --- a/chip/mt8192_scp/ipi_chip.h +++ b/chip/mt8192_scp/ipi_chip.h @@ -15,6 +15,7 @@ /* * Video decoder supported capability */ +#define VCODEC_CAPABILITY_4K_DISABLED BIT(4) #define VDEC_CAP_MM21 BIT(5) #define VDEC_CAP_MT21C BIT(6) #define VDEC_CAP_H264_SLICE BIT(8) |