diff options
| author | Poornima Tom <poornima.tom@intel.com> | 2021-03-08 16:32:52 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-05-27 07:53:51 +0000 |
| commit | ebc24d5a67eb0101f31334cf211f6cdf8d84f57a (patch) | |
| tree | becba5a2ee109ee47e9bf951346993d65bc61e60 | |
| parent | 9a30ce07ee553a753a5d0340b7743f64e340a38c (diff) | |
| download | chrome-ec-ebc24d5a67eb0101f31334cf211f6cdf8d84f57a.tar.gz | |
adlrvp: Add dual retimer configuration
DDR5 based sku has dual retimer based topology for port0 & port1.
Identify DDR5 board & reconfigure usbmux at run time to support
dual retimer topology.
BUG=b:189190982
BRANCH=none
TEST=Able to configure the retimers and TBT is detected.
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Change-Id: I0ff859f7770a6c55931d413b2ea366d4f6aafe84
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2712214
Reviewed-by: caveh jalali <caveh@chromium.org>
| -rw-r--r-- | baseboard/intelrvp/adlrvp.c | 33 | ||||
| -rw-r--r-- | baseboard/intelrvp/adlrvp.h | 9 |
2 files changed, 42 insertions, 0 deletions
diff --git a/baseboard/intelrvp/adlrvp.c b/baseboard/intelrvp/adlrvp.c index b5fa260c9f..fcb590b16e 100644 --- a/baseboard/intelrvp/adlrvp.c +++ b/baseboard/intelrvp/adlrvp.c @@ -152,6 +152,25 @@ struct usb_mux usb_muxes[] = { }; BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); +/* USB Mux Configuration for Soc side BB-Retimers for Dual retimer config */ +struct usb_mux soc_side_bb_retimer0_usb_mux = { + .usb_port = TYPE_C_PORT_0, + .next_mux = &usbc0_tcss_usb_mux, + .driver = &bb_usb_retimer, + .i2c_port = I2C_PORT_TYPEC_0, + .i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR, +}; + +#if defined(HAS_TASK_PD_C1) +struct usb_mux soc_side_bb_retimer1_usb_mux = { + .usb_port = TYPE_C_PORT_1, + .next_mux = &usbc1_tcss_usb_mux, + .driver = &bb_usb_retimer, + .i2c_port = I2C_PORT_TYPEC_1, + .i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR, +}; +#endif + const struct bb_usb_control bb_controls[] = { [TYPE_C_PORT_0] = { .retimer_rst_gpio = IOEX_USB_C0_BB_RETIMER_RST, @@ -295,6 +314,20 @@ static void configure_retimer_usbmux(void) #endif break; + case ADLP_DDR5_RVP_SKU_BOARD_ID: + /* + * ADL-P-DDR5 RVP has dual BB-retimers for port0 & port1. + * Change the default usb mux config on runtime to support + * dual retimer topology. + */ + usb_muxes[TYPE_C_PORT_0].next_mux + = &soc_side_bb_retimer0_usb_mux; +#if defined(HAS_TASK_PD_C1) + usb_muxes[TYPE_C_PORT_1].next_mux + = &soc_side_bb_retimer1_usb_mux; +#endif + break; + /* Add additional board SKUs */ default: diff --git a/baseboard/intelrvp/adlrvp.h b/baseboard/intelrvp/adlrvp.h index 0c9ffb546e..9548498bb9 100644 --- a/baseboard/intelrvp/adlrvp.h +++ b/baseboard/intelrvp/adlrvp.h @@ -14,6 +14,7 @@ #include "baseboard.h" /* RVP Board ids */ +#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 #define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 #define ADL_RVP_BOARD_ID(id) ((id) & 0x3F) @@ -63,6 +64,8 @@ /* Config BB retimer */ #define CONFIG_USBC_RETIMER_INTEL_BB + +/* Connector side BB retimers */ #define I2C_PORT0_BB_RETIMER_ADDR 0x56 #if defined(HAS_TASK_PD_C1) #define I2C_PORT1_BB_RETIMER_ADDR 0x57 @@ -74,6 +77,12 @@ #define I2C_PORT3_BB_RETIMER_ADDR 0x59 #endif +/* SOC side BB retimers (dual retimer config) */ +#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 +#if defined(HAS_TASK_PD_C1) +#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 +#endif + /* Configure mux at runtime */ #define CONFIG_USB_MUX_RUNTIME_CONFIG |