NPCX: Convert keyboard pins to use ALTERNATE macro

Previously the keyboard row and column pins could not use the GPIO
alternate function mechanism because their DEVALT bits were inverted
with respect to all of the others, making it impossible to correctly
configure them.  With the refactor of the GPIO driver we can now add
the keyboard DEVALT entries to the gpio_alt_table, and use the
ALTERNATE macro and associated APIs to control the keyboard pin states.

The Wheatley RO firmware image is still 320 bytes smaller than before
the GPIO refactor.

Signed-off-by: Anton Staaf <robotboy@chromium.org>

BRANCH=None
BUG=None
TEST=make buildall -j
     Ran on Wheatley, manually verified keyboard functionality

Change-Id: Id04bc010834b5d95050b03ace6b0e1c5690757bf
Reviewed-on: https://chromium-review.googlesource.com/329762
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>

7 files changed, 67 insertions, 39 deletions

diff --git a/board/npcx_evb/gpio.inc b/board/npcx_evb/gpio.inc
index ee6013e2bd..03e3fcc071 100644
--- a/board/npcx_evb/gpio.inc
+++ b/board/npcx_evb/gpio.inc
@@ -45,9 +45,6 @@ GPIO(I2C3_SDA,      PIN(D, 0), GPIO_ODR_HIGH)
 GPIO(BOARD_VERSION1,       PIN(6, 4), GPIO_INPUT)    /* Board version stuffing resistor 1 */
 GPIO(BOARD_VERSION2,       PIN(6, 5), GPIO_INPUT)    /* Board version stuffing resistor 2 */
 GPIO(BOARD_VERSION3,       PIN(6, 6), GPIO_INPUT)    /* Board version stuffing resistor 3 */
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-GPIO(KBD_KSO2,             PIN(1, 7), GPIO_OUT_LOW)  /* Negative edge triggered keyboard irq. */
-#endif
 
 /**************************** Alternate pins for UART/I2C/ADC/SPI/PWM/MFT ****************************/
 /* Alternate pins for UART/I2C/ADC/SPI/PWM/MFT */
@@ -74,3 +71,12 @@ ALTERNATE(PIN_MASK(9, 0x08), 3,  MODULE_PWM,         0)    /* MFT-1/TA1_TACH1 fo
 ALTERNATE(PIN_MASK(4, 0x01), 3,  MODULE_PWM,         0)    /* MFT-1/TA1_TACH1 for FAN Test GPIO40  */
 #endif
 #endif
+
+/* Keyboard Columns */
+ALTERNATE(PIN_MASK(0, 0xE0), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(1, 0xFF), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(2, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
+
+/* Keyboard Rows */
+ALTERNATE(PIN_MASK(2, 0xFC), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(3, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
diff --git a/board/npcx_evb_arm/gpio.inc b/board/npcx_evb_arm/gpio.inc
index dd169a1806..c4aeed25ae 100644
--- a/board/npcx_evb_arm/gpio.inc
+++ b/board/npcx_evb_arm/gpio.inc
@@ -46,9 +46,6 @@ GPIO(I2C3_SDA,      PIN(D, 0), GPIO_ODR_HIGH)
 GPIO(BOARD_VERSION1,       PIN(6, 4), GPIO_INPUT)    /* Board version stuffing resistor 1 */
 GPIO(BOARD_VERSION2,       PIN(6, 5), GPIO_INPUT)    /* Board version stuffing resistor 2 */
 GPIO(BOARD_VERSION3,       PIN(6, 6), GPIO_INPUT)    /* Board version stuffing resistor 3 */
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-GPIO(KBD_KSO2,             PIN(1, 7), GPIO_OUT_LOW)  /* Negative edge triggered keyboard irq. */
-#endif
 
 /**************************** Alternate pins for UART/I2C/ADC/SPI/PWM/MFT ****************************/
 /* Alternate pins for UART/I2C/ADC/SPI/PWM/MFT */
@@ -75,3 +72,12 @@ ALTERNATE(PIN_MASK(9, 0x08), 3,  MODULE_PWM,         0)    /* MFT-1/TA1_TACH1 fo
 ALTERNATE(PIN_MASK(4, 0x01), 3,  MODULE_PWM,         0)    /* MFT-1/TA1_TACH1 for FAN Test GPIO40  */
 #endif
 #endif
+
+/* Keyboard Columns */
+ALTERNATE(PIN_MASK(0, 0xE0), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(1, 0xFF), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(2, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
+
+/* Keyboard Rows */
+ALTERNATE(PIN_MASK(2, 0xFC), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(3, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
diff --git a/board/wheatley/board.c b/board/wheatley/board.c
index c556741dd9..537214b0d7 100644
--- a/board/wheatley/board.c
+++ b/board/wheatley/board.c
@@ -406,6 +406,17 @@ void board_set_gpio_hibernate_state(void)
 	/* Change GPIOs' state in hibernate for better power consumption */
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
 		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
+
+	gpio_config_module(MODULE_KEYBOARD_SCAN, 0);
+
+	/*
+	 * Calling gpio_config_module sets disabled alternate function pins to
+	 * GPIO_INPUT.  But to prevent keypresses causing leakage currents
+	 * while hibernating we want to enable GPIO_PULL_UP as well.
+	 */
+	gpio_set_flags_by_mask(0x2, 0x03, GPIO_INPUT | GPIO_PULL_UP);
+	gpio_set_flags_by_mask(0x1, 0xFF, GPIO_INPUT | GPIO_PULL_UP);
+	gpio_set_flags_by_mask(0x0, 0xE0, GPIO_INPUT | GPIO_PULL_UP);
 }
 
 /* Any wheatley boards post version 2 should have ROP_LDO_EN stuffed. */
diff --git a/board/wheatley/gpio.inc b/board/wheatley/gpio.inc
index c3b9db8cff..8d16b9d817 100644
--- a/board/wheatley/gpio.inc
+++ b/board/wheatley/gpio.inc
@@ -149,3 +149,11 @@ ALTERNATE(PIN_MASK(4, 0x16), 1,  MODULE_ADC,       0)   /* ADC1/ADC3/ADC4 for AD
 ALTERNATE(PIN_MASK(B, 0x80), 3,  MODULE_POWER_LED, 0)   /* PWM5 for CHARGE_LED1 */
 ALTERNATE(PIN_MASK(C, 0x01), 3,  MODULE_POWER_LED, 0)   /* PWM6 for CHARGE_LED2 */
 
+/* Keyboard Columns */
+ALTERNATE(PIN_MASK(0, 0xE0), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(1, 0xFF), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(2, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
+
+/* Keyboard Rows */
+ALTERNATE(PIN_MASK(2, 0xFC), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(3, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c
index 4656d0b6e7..1ebf11e26c 100644
--- a/chip/npcx/gpio.c
+++ b/chip/npcx/gpio.c
@@ -278,6 +278,34 @@ const struct gpio_alt_map gpio_alt_table[] = {
 	{ NPCX_GPIO(4, 0),  NPCX_ALT(3, TA1_TACH1_SL1)},/* TA1_TACH1 */
 	{ NPCX_GPIO(A, 4),  NPCX_ALT(3, TB1_TACH2_SL1)},/* TB1_TACH2 */
 #endif
+	/* Keyboard Scan Module (Inputs) */
+	{ NPCX_GPIO(3, 1),  NPCX_ALT_INV(7, NO_KSI0_SL)},/* KSI0 */
+	{ NPCX_GPIO(3, 0),  NPCX_ALT_INV(7, NO_KSI1_SL)},/* KSI1 */
+	{ NPCX_GPIO(2, 7),  NPCX_ALT_INV(7, NO_KSI2_SL)},/* KSI2 */
+	{ NPCX_GPIO(2, 6),  NPCX_ALT_INV(7, NO_KSI3_SL)},/* KSI3 */
+	{ NPCX_GPIO(2, 5),  NPCX_ALT_INV(7, NO_KSI4_SL)},/* KSI4 */
+	{ NPCX_GPIO(2, 4),  NPCX_ALT_INV(7, NO_KSI5_SL)},/* KSI5 */
+	{ NPCX_GPIO(2, 3),  NPCX_ALT_INV(7, NO_KSI6_SL)},/* KSI6 */
+	{ NPCX_GPIO(2, 2),  NPCX_ALT_INV(7, NO_KSI7_SL)},/* KSI7 */
+	/* Keyboard Scan Module (Outputs) */
+	{ NPCX_GPIO(2, 1),  NPCX_ALT_INV(8, NO_KSO00_SL)},/* KSO00 */
+	{ NPCX_GPIO(2, 0),  NPCX_ALT_INV(8, NO_KSO01_SL)},/* KSO01 */
+	{ NPCX_GPIO(1, 7),  NPCX_ALT_INV(8, NO_KSO02_SL)},/* KSO02 */
+	{ NPCX_GPIO(1, 6),  NPCX_ALT_INV(8, NO_KSO03_SL)},/* KSO03 */
+	{ NPCX_GPIO(1, 5),  NPCX_ALT_INV(8, NO_KSO04_SL)},/* KSO04 */
+	{ NPCX_GPIO(1, 4),  NPCX_ALT_INV(8, NO_KSO05_SL)},/* KSO05 */
+	{ NPCX_GPIO(1, 3),  NPCX_ALT_INV(8, NO_KSO06_SL)},/* KSO06 */
+	{ NPCX_GPIO(1, 2),  NPCX_ALT_INV(8, NO_KSO07_SL)},/* KSO07 */
+	{ NPCX_GPIO(1, 1),  NPCX_ALT_INV(9, NO_KSO08_SL)},/* KSO08 */
+	{ NPCX_GPIO(1, 0),  NPCX_ALT_INV(9, NO_KSO09_SL)},/* KSO09 */
+	{ NPCX_GPIO(0, 7),  NPCX_ALT_INV(9, NO_KSO10_SL)},/* KSO10 */
+	{ NPCX_GPIO(0, 6),  NPCX_ALT_INV(9, NO_KSO11_SL)},/* KSO11 */
+	{ NPCX_GPIO(0, 5),  NPCX_ALT_INV(9, NO_KSO12_SL)},/* KSO12 */
+	{ NPCX_GPIO(0, 4),  NPCX_ALT_INV(9, NO_KSO13_SL)},/* KSO13 */
+	{ NPCX_GPIO(8, 2),  NPCX_ALT_INV(9, NO_KSO14_SL)},/* KSO14 */
+	{ NPCX_GPIO(8, 3),  NPCX_ALT_INV(9, NO_KSO15_SL)},/* KSO15 */
+	{ NPCX_GPIO(0, 3),  NPCX_ALT_INV(A, NO_KSO16_SL)},/* KSO16 */
+	{ NPCX_GPIO(B, 1),  NPCX_ALT_INV(A, NO_KSO17_SL)},/* KSO17 */
 };
 
 /*****************************************************************************/
@@ -557,21 +585,6 @@ void gpio_pre_init(void)
 	int flags;
 	int i, j;
 
-	uint32_t ksi_mask = (~((1<<KEYBOARD_ROWS)-1)) & KB_ROW_MASK;
-	uint32_t kso_mask = ((~((1<<KEYBOARD_COLS)-1))
-			<< CONFIG_KEYBOARD_KSO_BASE) & KB_COL_MASK;
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	kso_mask |= 1 << (CONFIG_KEYBOARD_KSO_BASE + 2);
-#endif
-
-	/* Set necessary pin mux to GPIO first */
-	/* Pin_Mux for KSO0-17 & KSI0-7 */
-	NPCX_DEVALT(ALT_GROUP_7)  = (uint8_t)(ksi_mask);
-	NPCX_DEVALT(ALT_GROUP_8)  = (uint8_t)(kso_mask);
-	NPCX_DEVALT(ALT_GROUP_9)  = (uint8_t)(kso_mask >> 8);
-	NPCX_DEVALT(ALT_GROUP_A) |= (uint8_t)(kso_mask >> 16);
-
 	/* Pin_Mux for FIU/SPI (set to GPIO) */
 	SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
 	SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
diff --git a/chip/npcx/keyboard_raw.c b/chip/npcx/keyboard_raw.c
index b52ab61b53..d68c9b1d45 100644
--- a/chip/npcx/keyboard_raw.c
+++ b/chip/npcx/keyboard_raw.c
@@ -9,6 +9,7 @@
 #include "keyboard_raw.h"
 #include "keyboard_scan.h"
 #include "clock.h"
+#include "gpio.h"
 #include "registers.h"
 #include "task.h"
 
@@ -40,13 +41,7 @@ void keyboard_raw_init(void)
 	NPCX_KBSOUT0 = 0x00;
 	NPCX_KBSOUT1 = 0x00;
 
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	/*
-	 * When column 2 is inverted, Nuvoton EC KBS outputs only support
-	 * open-drain. So we should change this pin to GPIO
-	 */
-	SET_BIT(NPCX_DEVALT(ALT_GROUP_8), NPCX_DEVALT8_NO_KSO02_SL);
-#endif
+	gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
 
 	/*
 	 * Enable interrupts for the inputs.  The top-level interrupt is still
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 6cd805d9f9..dd4ca3dbed 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -312,17 +312,6 @@ void system_set_gpios_and_wakeup_inputs_hibernate(void)
 		}
 	}
 
-	/*
-	 * Set all KBSOUTs to GPIOs and switch their mode to input and pull-up.
-	 * Otherwise pressing the keyboard matrix might cause some current
-	 * leakage during hibernating.
-	 */
-	NPCX_DEVALT(0x8) = 0xFF;
-	NPCX_DEVALT(0x9) |= 0x1F;
-	gpio_set_flags_by_mask(0x2, 0x03, GPIO_INPUT | GPIO_PULL_UP);
-	gpio_set_flags_by_mask(0x1, 0xFF, GPIO_INPUT | GPIO_PULL_UP);
-	gpio_set_flags_by_mask(0x0, 0xF0, GPIO_INPUT | GPIO_PULL_UP);
-
 	/* Enable wake-up inputs of hibernate_wake_pins array */
 	for (i = 0; i < hibernate_wake_pins_used; i++)
 		gpio_reset(hibernate_wake_pins[i]);